16-Bit, 20 KHz A/D Converter
5102ALP
7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling
edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after HOLD is latched.
8. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid t
dss
time after
the next falling SCLK.
T
ABLE
5. 5102ALP D
IGITAL
C
HARACTERISTICS
(T
A
= T
MIN TO
T
MA
X; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%)
P
ARAMETER
Calibration Memory Retention Power Supply Voltage
VA+ & VD+
1
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
2
Low-Level Output Voltage - I
OUT
= 1.6 mA
Input Leakage Current
Digital Output Pin Capacitance
S
YMBOL
V
MR
V
IH
V
IL
V
OH
V
OL
I
IN
C
OUT
M
IN
2.0
2.0
--
(VD+) -1.0
--
--
--
T
YP
--
--
--
--
--
--
9
M
AX
--
--
0.8
--
0.4
10
--
U
NIT
V
V
V
V
V
µA
pF
Memory
1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive.
AIN1, AIN2 or V
REF
must not be greater than VA+ or VD+. This parameter is guaranteed by characterization.
2. I
OUT
= -100 µ A. This specification guarantees TTL compatibility (V
OH
= 2.4V @ I
OUT
= -40 µ A.
LPT™ O
PERATION
Latchup Protection Technology (LPT™) automatically detects an increase in the supply current of the 5102ALP con-
verter due to a single event effect and internally cycle the power to the converter off, then on, which restores the
steady state operation of the device.
If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and
individual pull up resistors to the supply voltage (if used on the data bus) must no be less than 10 K ohm typical to
assure proper single event effect recovery.
STATUS can also be used to generate an input to the system data processor indicating that an LPT™ cycle has
occurred, and the protected device output accuracy may not be met until after the respective recovery time to the
event. The STATUS signal is generated from an advanced CMOS logic gate output. This output may not exhibit a
monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decou-
pling capacitance is charged. Loading on the STATUS output should be minimized because this signal is used inter-
nally by the 5102ALP. It is recommended that load current not exceed 2 mA and load capacitance be kept will below
1000 pF.
01.17.05 R
EV
3
All data sheets are subject to change without notice
6
©2005 Maxwell Technologies Inc.
All rights reserved.
MAXWELL [ MAXWELL TECHNOLOGIES ]
