MX25L4006E
(3) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence is shown as
Figure 13.
The definition of the status register bits is as below:
WIP bit.
The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit.
The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction.
BP2, BP1, BP0 bits.
The Block Protect (BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area(as de-
fined in table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be
executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be
executed)
SRWD bit.
The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-
tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1
and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP2, BP1, BP0) are read only.
bit 7
SRWD Status
Register
Write Protect
1= status
register write
disable
bit 6
0
bit 5
0
bit 4
BP2
(the level of
protected
block)
(note 1)
bit 3
bit 2
bit 1
bit 0
BP1
BP0
(the level
(the level
WEL (write WIP (write in
of protected of protected enable latch) progress bit)
block)
block)
1=write
1=write
enable
operation
(note 1)
(note 1)
0=not write 0=not in write
enable
operation
0
0
Note:
1. See the table "Protected Area Sizes".
P/N: PM1576
13
REV. 1.3, FEB. 10, 2012
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