1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Mo d e Re g ist e rs
Mode registers (MR0–MR3) are used to define various modes of programmable opera-
tions of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER
SET (MRS) command during initialization, and it retains the stored information (except
for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or
until the device loses power.
Contents of a mode register can be altered by reexecuting the MRS command. If the user
chooses to modify only a subset of the mode register’s variables, all variables must be
programmed when the MRS command is issued. Reprogramming the mode register will
not alter the contents of the memory array, provided it is performed correctly.
The MRS command can only be issued (or reissued) when all banks are idle and in the
t
precharged state ( RP is satisfied and no data bursts are in progress). After an MRS
t
t
command has been issued, two parameters must be satisfied: MRD and MOD.
t
The controller must wait MRD before initiating any subsequent MRS commands (see
Figure 52).
t
Fig u re 52: MRS-t o -MRS Co m m a n d Tim in g ( MRD)
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
1
2
MRS
NOP
NOP
NOP
NOP
MRS
Command
t
MRD
Address
Valid
Valid
3
CKE
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN) must
be satisfied, and no data bursts can be in progress.
2. tMRD specifies the MRS-to-MRS command minimum cycle time.
3. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see "Power-
Down Mode" on page 151).
t
4. For a CAS latency change, XPDLL timing must be met before any nonMRS command.
t
The controller must also wait MOD before initiating any nonMRS commands
(excluding NOP and DES), as shown in Figure 53 on page 109. The DRAM requires MOD
t
in order to update the requested features, with the exception of DLL RESET, which
t
requires additional time. Until MOD has been satisfied, the updated features are to be
assumed unavailable.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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