1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
t
Fig u re 53: MRS-t o -n o n MRS Co m m a n d Tim in g ( MOD)
T0
T1
T2
Ta0
Ta1
Ta2
CK#
CK
non
MRS
NOP
NOP
NOP
NOP
Command
MRS
t
MOD
Address
CKE
Valid
Valid
Valid
Old
setting
New
setting
Updating setting
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. Prior to issuing the MRS command, all banks must be idle (they must be precharged, tRP
must be satisfied, and no data bursts can be in progress).
t
2. Prior to Ta2 when MOD (MIN) is being satisfied, no commands (except NOP/DES) may be
issued.
3. If RTT was previously enabled, ODT must be registered LOW at T0 so that ODTL is satisfied
prior to Ta1. ODT must also be registered LOW at each rising CK edge from T0 until
tMOD (MIN) is satisfied at Ta2.
4. CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN), at which time
power-down may occur (see "Power-Down Mode" on page 151).
Mo d e Re g ist e r 0 (MR0)
The base register, MR0, is used to define various DDR3 SDRAM modes of operation.
These definitions include the selection of a burst length, burst type, CAS latency, oper-
ating mode, DLL RESET, write recovery, and precharge power-down mode, as shown in
Figure 54 on page 110.
Bu rst Le n g t h
Burst length is defined by MR0[1: 0] (see Figure 54 on page 110). Read and write accesses
to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to
“4” (chop mode), “8” (fixed), or selectable using A12 during a READ/ WRITE command
(on-the-fly). The burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to “01”
during a READ/ WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If
A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between
READ/ WRITE, are shown in the READ/ WRITE sections of this document.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A[i:2] when the burst length is set to “4” and by A[i:3] when the
burst length is set to “8” (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both READ
and WRITE bursts.
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1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
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109
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