1Gb : x4, x8, x16 DDR3 SDRAM
Fu n ct io n a l De scrip t io n
Fu n ct io n a l De scrip t io n
The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/ O pins. A single read or write
access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-
cycle data transfers at the I/ O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control,
command, and address signals are registered at every positive edge of CK. Input data is
registered on the first rising edge of DQS after the WRITE preamble, and output data is
referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE commands are used to select the
bank and the starting column location for the burst access.
DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row
precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Ge n e ra l No t e s
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise.
• The terms “DQS” and “CK” found throughout the data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document, and any
page or diagram may have been simplified to convey a topic and may not be inclusive
of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated herewithin is considered undefined, illegal,
and not supported and can result in unknown operation.
• Row addressing is denoted as A[n:0](1Gb: n = 12 [x16]; 1Gb: n = 13 [x4, x8]).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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