1Gb : x4, x8, x16 DDR3 SDRAM
Fu n ct io n a l Blo ck Dia g ra m s
Fig u re 4:
128 Me g x 8 Fu n ct io n a l Blo ck Dia g ra m
ODT
control
ODT
ZQ
To ODT/output drivers
ZQ CAL
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
VSSQ
A12
CK, CK#
CS#
VDDQ/2
BC4 (burst chop)
RTT_NOM
RTT_WR
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
RAS#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
CK, CK#
OTF
sw2
sw1
CAS#
WE#
DLL
(1 . . . 8)
Refresh
counter
DQ8
14
READ
FIFO
and
data
MUX
TDQS#
Mode registers
16
Bank 0
memory
array
Bank 0
Row-
address
MUX
8
14
64
DQ[7:0]
DQS, DQS#
row-
address
latch
READ
drivers
16,384
DQ[7:0]
(16,384 x 128 x 64)
14
and
decoder
VDDQ/2
Sense amplifiers
64
BC4
RTT_NOM
RTT_WR
8,192
BC4
OTF
sw2
sw1
I/O gating
3
DM mask logic
DQS, DQS#
(1, 2)
Bank
control
logic
A[13:0]
BA[2:0]
Address
register
17
3
V
DDQ/2
(128
x64)
WRITE
drivers
and
input
logic
8
64
RTT_NOM
RTT_WR
Data
interface
Data
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
DM/TDQS
(shared pin)
10
Columns 0, 1, and 2
CK, CK#
Column
2
(select upper or
lower nibble for BC4)
Fig u re 5:
64 Me g x 16 Fu n ct io n a l Blo ck Dia g ra m
ODT
control
ODT
ZQ
ZQ CAL
To ODT/output drivers
RESET#
CKE
RZQ
Control
logic
ZQCL, ZQCS
VSSQ
A12
CK, CK#
CS#
V
DDQ/2
BC4 (burst chop)
RTT_NOM
RTT_WR
Column 0, 1, and 2
Bank
Bank
7
RAS#
Bank
Bank
Bank
Bank
Bank
Bank
Bank
7
CK, CK#
OTF
6
6
sw2
sw1
Bank
5
CAS#
5
Bank
Bank
Bank
Bank
4
4
3
WE#
3
DLL
2
2
(1 . . . 16)
1
1
Refresh
counter
13
READ
FIFO
and
data
MUX
Mode registers
16
Bank
0
Bank
0
Row-
address
MUX
16
13
128
DQ[15:0]
LDQS, LDQS#, UDQS, UDQS#
memory
array
row-
address
latch
READ
drivers
DQ[15:0]
8,192
(8192 x 128 x 128)
13
and
decoder
V
DDQ/2
Sense amplifiers
16,384
BC4
128
RTT_NOM
RTT_WR
sw2
BC4
OTF
sw1
LDQS, LDQS#
UDQS, UDQS#
I/O gating
DM mask logic
3
Bank
control
logic
(1 . . . 4)
A[12:0]
BA[2:0]
Address
register
16
3
VDDQ/2
(128
WRITE
drivers
and
input
logic
x128)
128
16
Data
RTT_NOM
Data
interface
RTT_WR
sw2
Column
decoder
sw1
Column-
address
counter/
latch
7
3
LDM/UDM
10
(1, 2)
Columns 0, 1, and 2
Column
(select upper or
lower nibble for BC4)
2
CK, CK#
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
13
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