Fig u re 65: MPR Syst e m Re a d Ca lib ra t io n w it h BC4: Up p e r Nib b le , Th e n Lo w e r Nib b le
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Td
T0
Ta
Tb
CK#
CK
1
1
Command
PREA
MRS
READ
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MRS
NOP
NOP
Valid
t
t
t
t
MOD
t
RF
CCD
MPRR
MOD
Bank address
3
0
Valid
Valid
3
2
0
2
0
A[1:0]
Valid
3
1
4
0
A2
1
0
A[9:3]
A10/AP
A11
00
0
Valid
Valid
Valid
Valid
Valid
Valid
00
0
1
0
0
1
1
A12/BC#
0
0
0
0
Valid
Valid
A[15:13]
Valid
Valid
RL
DQS, DQS#
RL
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BC4 either by MRS or OTF.
2. Memory controller must drive 0 on A[1:0].
3. A2 = 1 selects upper 4 nibble bits 4 . . . 7.
4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
MDTIC [ Micon Design Technology Corporation ]
