Fig u re 63: MPR Syst e m Re a d Ca lib ra t io n w it h BL8: Fixe d Bu rst Ord e r, Ba ck-t o -Ba ck Re a d o u t
T0
Ta
Tb
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
MRS
Td
CK#
CK
1
1
Command
PREA
MRS
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Valid
READ
READ
t
t
t
MPRR
t
t
MOD
CCD
RP
MOD
Bank address
A[1:0]
3
0
Valid
Valid
3
2
0
2
0
Valid
2
0
2
1
A2
1
0
00
0
A[9:3]
00
0
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
A10/AP
A11
1
0
0
1
A12/BC#
A[15:13]
0
0
Valid
0
Valid
0
RL
DQS, DQS#
RL
DQ
Indicates A Break in
Time Scale
Don’t Care
Notes: 1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].