1Gb : x4, x8, x16 DDR3 SDRAM
Op e ra t io n s
Fig u re 86: Writ e Bu rst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
1
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
WL = AL + CWL
Bank,
2
Address
Col n
t
t
t
t
t
DQSS
DSH
DSH
DSH
DSH
t
t
t
WPRE
t
WPST
DQSL
t
DQSS (MIN)
DQS, DQS#
t
t
t
t
t
t
t
t
DQSL
DQSH
DQSH
DQSL DQSH
DQSL DQSH
DQSL DQSH
DI
DI
n + 1
DI
DI
DI
DI
DI
DI
n + 7
3
DQ
n
n + 2
n + 3
n + 4
n + 5
n + 6
t
t
t
t
DSH
DSH
DSH
DSH
t
t
t
WPRE
t
WPST
t
DQSS (NOM)
DQS, DQS#
t
t
t
t
t
t
t t
DQSL DQSH
DQSL
DQSH
DQSL
DQSH
DQSL DQSH
DQSL DQSH
t
t
t
t
t
DSS
DSS
DSS
DSS
DSS
DI
DI
DI
n + 2
DI
n + 3
DI
n + 4
DI
n + 5
DI
DI
n + 7
3
DQ
n
n + 1
n + 6
t
DQSS
t
t
WPRE
t
t
WPST
DQSS (MAX)
DQS, DQS#
t
t
t
t
t
t
t
t
t
t
t
t
DQSL
DQSH
DQSL
DQSH
DQSL DQSH
DQSL DQSH
DQSL DQSH
t
t
DSS
DSS
DSS
DSS
DSS
DI
DI
n + 1
DI
DI
n + 3
DI
DI
n + 5
DI
DI
3
DQ
n
n + 2
n + 4
n + 6
n + 7
Transitioning Data
Don’t Care
Notes: 1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the
WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5. tDQSS must be met at each rising clock edge.
t
6. tWPST is usually depicted as ending at the crossing of DQS, DQS#; however, WPST actually
ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_4.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
141
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