1Gb : x4, x8, x16 DDR3 SDRAM
Ba ll Assig n m e n t s a n d De scrip t io n s
Fig u re 8:
96-Ba ll FBGA – x16 Ba ll Assig n m e n t s (To p Vie w )
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ13
VDD
DQ15
VSS
DQ12
VDDQ
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
UDQS# DQ14
UDQS DQ10
DQ11
VDDQ
VSSQ
DQ2
DQ9
UDM
DQ0
LDQS
LDQS#
DQ4
RAS#
CAS#
WE#
BA2
A0
DQ8
LDM
DQ1
VDD
VSSQ
VSSQ
DQ3
VSS
VDDQ
VSSQ
G
H
J
DQ6
VREFDQ VDDQ
DQ7
CK
DQ5
VSS
NC
ODT
NC
VSS
VDD
CS#
K
L
M
N
P
CK#
VDD
CKE
NC
A10/AP
NC
ZQ
VSS
BA0
A3
VREFCA
VSS
VDD
VSS
A12/BC# BA1
VDD
VSS
A5
A2
A1
A11
NC
A4
A6
A8
R
T
VDD
VSS
A7
A9
VDD
VSS
RESET#
NC
Notes: 1. Ball descriptions listed in Table 5 on page 21 are listed as “x4, x8” if unique; otherwise, x4
and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
3. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to
the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined
in Table 5 on page 21).
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
16
MDTIC [ Micon Design Technology Corporation ]
