Ta b le 81:
Sym b o l
Syn ch ro n o u s ODT Pa ra m e t e rs
De scrip t io n
De fin it io n fo r All DDR3
Sp e e d Bin s
Be g in s a t
De fin e d t o
Un it s
ODTL on
ODTL off
ODTH4
ODT synchronous turn-on delay
ODT synchronous turn-off delay
ODT registered HIGH
ODT registered HIGH
RTT_ON ±tAON
RTT_OFF ±tAOF
CWL + AL - 2
CWL + AL - 2
4tCK
tCK
tCK
tCK
ODT minimum HIGH time after ODT
assertion or WRITE (BC4)
ODT registered HIGH, or
write registration with ODT
HIGH
ODT registered LOW
ODTH8
tAON
tAOF
ODT minimum HIGH time after
WRITE (BL8)
Write registration with ODT
HIGH
ODT registered LOW
RTT_ON
6tCK
tCK
ps
ODT turn-on relative to ODTL on
completion
Completion of ODTL on
See Table 53 on page 67
0.5tCK ± 0.2tCK
ODT turn-off relative to ODTL off
completion
Completion of ODTL off
RTT_OFF
tCK
Fig u re 116: Syn ch ro n o u s ODT
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CK#
CK
CKE
AL = 3
AL = 3
CWL - 2
ODT
ODTH4 (MIN)
ODTL off = CWL + AL - 2
ODTL on = CWL + AL - 2
t
t
AON (MIN)
t
AOF (MIN)
t
RTT
RTT_NOM
AON (MAX)
AOF (MAX)
Transitioning
Don’t Care
Notes: 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. RTT_NOM is enabled.
MDTIC [ Micon Design Technology Corporation ]
