1Gb : x4, x8, x16 DDR3 SDRAM
On -Die Te rm in a t io n (ODT)
ODT Off Du rin g READs
As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled
at least one-half clock cycle before the READ preamble by driving the ODT ball LOW (if
either RTT_NOM or RTT_WR is enabled). RTT may not be enabled until the end of the post-
amble as shown in the example in Figure 118 on page 171.
Note:
ODT may be disabled earlier and enabled later than shown in Figure 118 on page 171.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
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