1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – IDD Sp e cifica t io n s a n d Co n d it io n s
Fig u re 16: IDD4R Exa m p le – DDR3-800, 5-5-5, x8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CK
BA[2:0]
0
1
2
3
A[9:0]
A10
000
3FF
000
3FF
A[12:11]
0
3
0
3
CS#
RAS#
CAS#
WE#
CMD[2:0]
RD
D
D#
D#
RD
D
D#
D#
RD
D
D#
D#
RD
D
DQ[7:0]
DM
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF
Start measurement loop
Notes: 1. Data DQ is shown, but the output buffer should be switched off (per MR1[12] = 1) to
achieve IOUT = 0mA (MR1[12] = 0 is reflected in this example; however, test conditions are
MR1[12] = 1). Address inputs are split into three parts.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_D2.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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