1Gb : x4, x8, x16 DDR3 SDRAM
Ele ct rica l Sp e cifica t io n s – DC a n d AC
Ele ct rica l Sp e cifica t io n s – DC a n d AC
DC Op e ra t in g Co n d it io n s
Ta b le 20:
DC Ele ct rica l Ch a ra ct e rist ics a n d Op e ra t in g Co n d it io n s
All voltages are referenced to VSS
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
No m
Ma x
Un it s No t e s
Supply voltage
VDD
VDDQ
II
1.425
1.425
–2
1.5
1.5
–
1.575
1.575
2
V
V
1, 2
1, 2
I/O supply voltage
Input leakage current
µA
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
IVREF
–1
–
1
µA
3, 4
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes: 1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC
(0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing
parameters.
3. VREF (see Table 21).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin
should be minimal.
In p u t Op e ra t in g Co n d it io n s
Ta b le 21:
DC Ele ct rica l Ch a ra ct e rist ics a n d In p u t Co n d it io n s
All voltages are referenced to VSS
Pa ra m e t e r/Co n d it io n
Sym b o l
Min
No m
Ma x
Un it s No t e s
Input reference voltage command/address bus
I/O reference voltage DQ bus
VREFCA(DC)
VREFDQ(DC)
VTT
0.49 × VDD
0.49 × VDD
–
0.5 × VDD
0.5 × VDD
0.5 × VDDQ
0.51 × VDD
0.51 × VDD
–
V
V
V
1, 2
2, 3
4
Command/address termination voltage
(system level, not direct DRAM input)
Notes: 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1
percent × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not
exceed ±2 percent of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifica-
tions if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1
percent × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not
exceed ±2 percent of VREFDQ(DC).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resis-
tors. MIN and MAX values are system-dependent.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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