1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
t
t
Fig u re 27: AONPD a n d AOFPD De fin it io n
t
t
AONPD
AOFPD
Begin point: Rising edge of CK - CK#
with ODT first registered HIGH
Begin point: Rising edge of CK - CK#
with ODT first registered LOW
CK
CK
VDDQ/2
CK#
CK#
t
t
AONPD
AOFPD
End point: Extrapolated point at VRTT_NOM
VRTT_NOM
TSW2
TSW2
TSW1
DQ, DM
TSW1
DQS, DQS#
TDQS, TDQS#
VSW2
VSW2
VSW1
VSW1
VSSQ
VSSQ
End point: Extrapolated point at VSSQ
t
Fig u re 28: ADC De fin it io n
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLCNW
Begin point: Rising edge of CK - CK# defined by
the end point of ODTLCWN4 or ODTLCWN8
CK
VDDQ/2
CK#
t
t
ADC
ADC
VRTT_NOM
VRTT_NOM
TSW21
TSW11
DQ, DM
DQS, DQS#
TDQS, TDQS#
End point:
Extrapolated
point at VRTT_NOM
TSW22
VSW2
TSW12
End point: Extrapolated point at VRTT_WR
VSW1
VRTT_WR
VSSQ
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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