1Gb : x4, x8, x16 DDR3 SDRAM
ODT Ch a ra ct e rist ics
Ta b le 30:
RTT Effe ct ive Im p e d a n ce s
MR1
[9, 6, 2]
RTT
Re sist o r
VOUT
Min
No m
Ma x
Un it s
0, 1, 0
0, 0, 1
0, 1, 1
1, 0, 1
1, 0, 0
120Ω
RTT
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
0.2 × VDDQ
0.5 × VDDQ
0.8 × VDDQ
VIL(AC) to VIH(AC)
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
0.6
0.9
0.9
0.9
0.9
0.6
0.9
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
1.1
1.1
1.4
1.4
1.1
1.1
1.6
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/1
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/2
RZQ/4
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/3
RZQ/6
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/4
RZQ/8
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/6
RZQ/12
120PD240
RTT
120PU240
120Ω
60Ω
40Ω
30Ω
20Ω
RTT
60PD120
60PU120
RTT
60Ω
RTT
RTT
40PD80
40PU80
40Ω
30Ω
20Ω
RTT
RTT
30PD60
30PU60
RTT
RTT
20PD40
20PU40
Notes: 1. Values assume an RZQ of 240Ω (±1 percent).
ODT Se n sit ivit y
If either the temperature or voltage changes after I/ O calibration, the tolerance limits
listed in Table 29 on page 49 and Table 30 can be expected to widen according to
Tables 31 and 32 on page 51.
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
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50
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