1Gb : x4, x8, x16 DDR3 SDRAM
Sp e e d Bin Ta b le s
Da t a Se t u p , Ho ld , a n d De ra t in g
t
t
The total DS (setup time) and DH (hold time) required is calculated by adding the data
t
t
sheet DS (base) and DH (base) values (see Table 58; values come from Table 53 on
t
t
page 67) to the Δ DS and Δ DH derating values (see Table 59 on page 85), respectively.
t
t
t
Example: DS (total setup time) = DS (base) + Δ DS. For a valid transition, the input
t
signal has to remain above/ below VIH(AC)/ VIL(AC) for some time VAC (see Table 61 on
page 86).
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached VIH[AC]/ VIL[AC]) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach VIH/
VIL(AC). For slew rates which fall between the values listed in Table 59 on page 85, the
derating values may obtained by linear interpolation.
t
Setup ( DS) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup ( DS) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC)
and the first crossing of VIL(AC) MAX. If the actual signal is always earlier than the
nominal slew rate line between the shaded “VREF(DC)-to-AC region,” use the nominal
slew rate for derating value (see Figure 39 on page 87). If the actual signal is later than
the nominal slew rate line anywhere between the shaded “VREF(DC)-to-AC region,” the
slew rate of a tangent line to the actual signal from the AC level to the DC level is used for
derating value (see Figure 41 on page 89).
t
Hold ( DH) nominal slew rate for a rising signal is defined as the slew rate between the
t
last crossing of VIL(DC) MAX and the first crossing of VREF(DC). Hold ( DH) nominal slew
rate for a falling signal is defined as the slew rate between the last crossing of
VIH(DC) MIN and the first crossing of VREF(DC). If the actual signal is always later than the
nominal slew rate line between the shaded “DC-to-VREF(DC) region,” use the nominal
slew rate for derating value (see Figure 40 on page 88). If the actual signal is earlier than
the nominal slew rate line anywhere between the shaded “DC-to-VREF(DC) region,” the
slew rate of a tangent line to the actual signal from the “DC-to-VREF(DC) region” is used
for derating value (see Figure 42 on page 90).
Ta b le 58:
Sym b o l
Da t a Se t u p a n d Ho ld Va lu e s a t 1 V/n s (DQS, DQS# a t 2 V/n s) – AC/DC-Ba se d
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Un it s
Re fe re n ce
tDS AC175 (base)
tDH AC175 (base)
tDS AC150 (base)
tDH AC150 (base)
75
150
–
25
100
–
–
–
–
–
ps
ps
ps
ps
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
VIH(AC)/VIL(AC)
VIH(DC)/VIL(DC)
30
65
10
45
–
–
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_3.fm - Rev. D 8/1/08 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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