Micrel, Inc.
SY89297U
Pin Description
Pin Number
1
2
3
Pin Name
INA
/INA
VTA
Pin Function
Channel A Differential Input: INA and /INA pins receive the Channel A data. QA and /QA are
the delayed product of INA and /INA. Each input is internally terminated to VTA through a 50Ω
resistor (100Ω across INA and /INA).
Input A Termination Center-Tap: Each side of the differential input pair terminates to this pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” section.
Input B Termination Center-Tap: Each side of the differential input pair terminates to this pin.
This pin provides a center-tap to a termination network for maximum interface flexibility. See
“Input Interface Applications” section.
Channel B Differential Input: INB and /INB pins receive the Channel B data. QB and /QB are
the delayed product of INB and /INB. Each input is internally terminated to VTB through a 50Ω
resistor (100Ω across INB and /INB).
Reference Voltage Output: For AC-coupled input signals, this pin can bias the inputs IN and /IN.
Connect VREF-AC directly to the VT input pin for each channel. De-couple to V
CC
using a
0.01µF capacitor. Maximum sink/source current is
±0.5mA.
For DC-coupled input applications,
leave VREF-AC pin floating.
Negative Supply: Exposed pad must be connected to a ground plane that is the same potential
as the ground pins.
CMOS/TTL-Compatible Enable Input: When the /ENA pin is pulled HIGH, QA is held LOW and
/QA goes HIGH after the programmed delay propagates through the part. /ENA contains a
67kΩ pull-down resistor and defaults LOW when left floating. Logic threshold level is V
CC
/2
CMOS/TTL-Compatible Enable Input: When the /ENB pin is pulled HIGH, QB is held LOW and
/QB goes HIGH after the programmed delay propagates through the part. /ENB contains a
67kΩ pull-down resistor and defaults LOW when left floating. Logic threshold level is Vcc/2
Power Supply: Bypass each supply pin with 0.1µF//0.01µF low-ESR capacitors. See DC
Electrical Characteristics table for more details. 2.5V
±5%
or 3.3V
±10%.
CML Differential Output: QB and /QB are the delayed product of INB, /INB. CML outputs are
terminated at the destination with 100Ω across the pair. See “CML Output Termination”
section.
CML Differential Output: QA and /QA are the delayed product of INA, /INA. CML outputs are
terminated at the destination with 100Ω across the pair. See “CML Output Termination”
section.
CMOS/TTL-compatible 3-pin serial programming control inputs: The 3-pin serial control sets
each channel’s IN to Q delay. DA(0:9) control channel A delay. DB(0:9) control channel B. To
program the two channels, insert a 20-bit word (DA0:DA9 and DB0:DB9) into SDATA and clock
in the control bits with SCLK. Maximum input frequency to SCLK is 40MHz. Data is loaded into
the serial registers on the L-H transition of SCLK. After all 20-bits are clocked in, SLOAD
latches the new delay bits. These pins have internal pull-downs at the inputs. See “AC
Electrical Characteristics” for delay values. Logic threshold level is Vcc/2. SCLK and SDATA
contain a 67kΩ pull-down resistor and default LOW when left floating.
CMOS/TTL-compatible 3-pin serial programming control input: SLOAD controls the latches that
transfer scanned data to the delay line. These latches are transparent when SLOAD is high.
Data transfers from the latch to the delay line on a L-H transition of SLOAD. SLOAD has to
transition H-L before new data is loaded in the scan chain. When SLOAD is high, the latches
are transparent and SCLK cannot switch. Otherwise, new data will immediately transfer to the
scan chain. Logic threshold level is Vcc/2. SLOAD contains a 67kΩ pull-down resistor and
defaults LOW when left floating.
CMOS/TTL-compatible output: This pin is used to support cascading multiple SY89297U delay
lines. Serial data is clocked into the SDATA input and is clocked out of SOUT into the next
SY89297U delay line. SOUT pin includes an internal 550Ω pull-up resistor.
4
5
6
VTB
INB
/INB
7
VREF-AC
GND,
Exposed Pad
/ENA
8, 11, 20
9
10
12, 15, 16, 19
13
14
17
18
/ENB
VCC
/QB
QB
/QA
QA
23
22
SCLK
SDATA
24
SLOAD
21
SOUT
December 2011
4
M9999-120211-C
hbwhelp@micrel.com
or (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
