Micrel, Inc.
SY89297U
AC Electrical Characteristics
(7)
T
A
=
−40°C
to +85°C, Channels A and B, unless otherwise stated.
Symbol
Parameter
Step Delay
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
D0-D9 High
Monotonic
INL
t
S
Hold Time
t
H
t
PW
t
R
t
JITTER
t
r
, t
f
Notes:
7.
8.
9.
High frequency AC electricals are guaranteed by design and characterization.
Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the crosspoint of the output.
INL (Integral Non-Linearity) is defined from its corresponding point on the ideal delay versus D[9:0] curve as the deviation from its ideal delay. The
maximum difference is the INL. Theoretical Ideal Linearity (TIL) = (measured maximum delay – measured minimum delay) ÷ 1023. INL = measured
delay – (measured minimum delay + (step number x TIL)).
Condition
Min.
Typ.
5
10
20
40
80
160
320
640
1280
2560
5115
Max.
Units
Δt
ps
−5
Note 9
−15
400
400
300
300
−100
200
1000
Note 14
Note 15
Note 16
Note 17
20% to 80% (Q)
Input Frequency = 1.6GHz
30
45
55
800
25
+15
ps
Integral Non-Linearity
Setup Time
SDATA to SCLK
SCLK to SLOAD
/EN to IN
SLOAD to SCLK
IN to /EN
SCLK to SDATA
Pulse Width
Release Time
Cycle-to-Cycle Jitter
Total Jitter
Random Jitter
Output Rise/Fall Time
Duty Cycle
SLOAD
/EN to IN
Note 10
Note 11
Note 12
Note 13
ps
ps
ps
ps
2
20
2
80
55
ps
RMS
ps
PP
ps
RMS
ps
%
10. SCLK has to transition L-H a setup time before the SLOAD H-L transition to ensure the valid data is properly latched. See timing diagram "Setup
and Hold Time: SCLK and SLOAD.”
11. This setup time is the minimum time that /EN must be asserted prior to the next transition of IN / /IN to prevent an output response greater than
±75
mV to that IN or /IN transition. See timing diagram Setup, Hold and Release Time: IN and /EN."
12. SCLK has to transition L-H a hold time after the SLOAD H-L transition to ensure that the valid data is properly latched before starting to load new
data. See timing diagram "Setup and Hold Time: SCLK and SLOAD.”
13. This hold time is the minimum time that /EN must remain asserted after a negative going transition of IN to prevent an output response greater than
+75mv to the IN transition. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
14. This release time is the minimum time that /EN must be de-asserted prior to the next IN / /IN transition to affect the propagation delay of IN to Q
less than 1ps. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
15. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.
T
jitter_cc
= T
n
– T
n
+1, where T is the time between rising edges of the output signal.
16. Total jitter definition: With an ideal clock input, no more than one output edge in 10
12
output edges will deviate by more than the specified peak-to-
peak jitter value.
17. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.
Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
December 2011
7
M9999-120211-C
hbwhelp@micrel.com
or (408) 955-1690
MICREL [ MICREL SEMICONDUCTOR ]
