ML6510
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS rise time, fall time and duty cycle are measured for a generic load; (see Load Conditions section).
tR
Rise time, LOAD [0-7] output
Fall time, LOAD [0-7] output
Input frequency, CLKIN pin
0.8 → 2.0V, 80MHz
2.0 → 0.8V, 80MHz
150
150
10
1500
1500
80
ps
ps
tF
fIN
fOUT
MHz
MHz
MHz
MHz
%
Output frequency , CLK [0-7]
output
ML6510-80
10
80
ML6510-130 (Note 2)
10
130
160
60
fVCO
DC
PLL VCO operating frequency
Output duty cycle
80
Measured at device load, at 1.5V
Cycle-to-cycle
40
tJITTER
Output jitter
75
150
11
ps
Peak-to-peak
ps
tLOCK
PLL and deskew lock time
After programming is complete
ms
SKEW CHARACTERISTICS All skew measurements are made at the load, at 1.5V threshold each output load can vary independently
within the specified range for a generic load (see Load Conditions section).
tSKEWR
tSKEWF
tSKEWIO
Output to output rising
edge skew, all clocks
500
1.5
ps
ns
ps
Output to output
falling edge skew
Output clock frequency ≥ 50MHz
CLKIN input to any
LOAD [0-7] output
rising edge skew
N = M = 0
600
N ≥ 2, M ≥ 2
1.25
ns
ns
tRANGE
tSKEWB
Round trip delay CLKX to FBX
pin; output CLK period = tCLK
Output frequency < 50MHz
Output frequency ≥ 50MHz
0
0
10
tCLK/2
Output-to-output rising
edge skew, between matched
loads
Providing first (see LOAD
conditions) order matching
order matching between outputs
250
ps
PART-TO-PART SKEW CHARACTERISTICS Skew measured at the loads, at 1.5V threshold. Reference clock output pins drive clock
input pins of another ML6510.
tPP1
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1 and
N = 0, M = 0; RCLK outputs to
CLKIN inputs distance less than 2"
1
1
ns
ns
tPP2
Total load-to-load skew between
multiple chips interfaced with
reference clock pins.
Slave chip CS = 1, CM = 1 and
N ≥ 2, M ≥ 2; RCLK outputs to
CLKIN inputs distance less than 2"
PROGRAMMING TIMING CHARACTERISTICS
tRESET
RESET assertion pulse
50
ns
width
tA1
tA2
tA3
AUX mode MCLK high time
AUX mode MCLK low time
2000
2000
10
ns
ns
ns
AUX mode MDOUT data
hold time
tA4
tA5
AUX mode MDOUT data
setup time
10
ns
ns
AUX mode MCLK period
5000
5
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
