ML6691
PIN CONFIGURATION
ML6691
44-PIN PLCC (Q44)
TXCLK
MDIO
41
TXEN
MDC
AD4
AD3
AD2
AD1
AD0
TXC
40
39 TSM4
38 TSM3
37 TSM2
36 TSM1
35 TSM0
34 SD
33 RSM4
32 RSM3
31 RSM2
30 RSM1
29 RSM0
18
RXDV
19 20
RXER
RXCLK
21
V
CC
22
DCFR
23
GND
24
LOCAL
25
RST
26
CS
27
LPBK
28
RXC
V
CC
1
6
TXER 7
TXD3 8
TXD2 9
TXD1 10
TXD0 11
CRS 12
COL 13
RXD3 14
RXD2 15
RXD1 16
RXD0 17
5
4
3
2
44
43
42
PIN DESCRIPTION
PIN#
NAME
FUNCTION
PIN#
NAME
FUNCTION
1,21
2,3,4,
43,44
V
CC
AD[4:0]
Positive 5 volt supply.
Local PHY address. These 5 inputs set
the address to which the local physical
layer responds. When an address
match is detected, the CS output is
asserted.
Transmit clock output. Continuous
25MHz clock provides the timing
reference for the transfer of TXEN,
TXER, and TXD[3:0] from the MAC.
TXCLK is generated from the TXC
input.
Transmit enable input. A logic high
enables the transmit section of the
ML6691. This signal indicates the
MAC is transmitting nibble-wide data.
TXEN is synchronous to TXCLK.
Transmit error input. When TXER is
high , while TXEN is asserted, the
ML6691 will insert an “H” symbol in
the data stream. TXER is synchronous
to TXCLK.
12
CRS
Carrier sense output. A logic high
indicates that either the transmit or
receive medium is non-idle. CRS is
deasserted when both transmit and
receive are idle.
Collision detect output. A logic high
indicates a collision (simultaneous
transmit and receive in half duplex
mode).
13
COL
5
TXCLK
14-17
6
TXEN
RXD[3:0] Receive nibble data outputs. Nibble-
wide data for transmission to the MAC.
RXD[0] is the least significant bit.
RXD[3:0] is synchronous to RXCLK.
RXDV
Receive data valid output. A logic high
indicates the ML6691 is presenting
valid nibble-wide data. RXDV shall
remain asserted from the first
recovered nibble of the frame through
the final recovered nibble. RXDV will
be de-asserted prior to the first RXCLK
that follows the final nibble. RXDV is
synchronous to RXCLK.
Receive error output. Active high,
indicates that a coding error was
detected. RXER is synchronous to
RXCLK.
18
7
TXER
8-11
TXD[3:0] Transmit nibble data inputs. Nibble-
wide data from the MAC. For data
transmission TXEN must be asserted.
TXD[0] is the least significant bit.
TXD[3:0] is synchronous to TXCLK.
19
RXER
2
MICRO-LINEAR [ MICRO LINEAR CORPORATION ]
