欢迎访问ic37.com |
会员登录 免费注册
发布采购

24LC21A 参数 Datasheet PDF下载

24LC21A图片预览
型号: 24LC21A
PDF下载: 下载PDF文件 查看货源
内容描述: 1K 2.5V双模式I 2 C串行EEPROM [1K 2.5V Dual Mode I 2 C Serial EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 18 页 / 241 K
品牌: MICROCHIP [ MICROCHIP TECHNOLOGY ]
 浏览型号24LC21A的Datasheet PDF文件第1页浏览型号24LC21A的Datasheet PDF文件第2页浏览型号24LC21A的Datasheet PDF文件第4页浏览型号24LC21A的Datasheet PDF文件第5页浏览型号24LC21A的Datasheet PDF文件第6页浏览型号24LC21A的Datasheet PDF文件第7页浏览型号24LC21A的Datasheet PDF文件第8页浏览型号24LC21A的Datasheet PDF文件第9页  
24LC21A
TABLE 1-2:
AC CHARACTERISTICS
Symbol
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
Vcc= 2.5-5.5V
Standard Mode
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
4000
4700
4000
4700
0
250
4000
4700
Max
100
1000
300
3500
Vcc= 4.5 - 5.5V
Fast Mode
Min
600
1300
600
600
0
100
600
1300
Max
400
300
300
900
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Remarks
Parameter
After this period the first clock
pulse is generated
Only relevant for repeated
Start condition
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppres- T
SP
sion (SDA and SCL pins)
Write cycle time
T
WR
Transmit-Only Mode Parameters
Output valid from VCLK
T
VAA
VCLK high time
T
VHIGH
VCLK low time
T
VLOW
VCLK setup time
T
VHST
VCLK hold time
T
SPVL
Mode transition time
T
VHZ
Transmit-only power-up
T
VPU
time
Input filter spike suppres- T
SPV
sion (VCLK pin)
Endurance
Note 1:
2:
3:
4:
4000
4700
0
4000
0
1M
250
50
10
2000
1000
100
20 + 0.1
C
B
600
1300
0
600
0
1M
250
50
10
1000
500
100
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
cycles
Time the bus must be free
before a new transmission
can start
C
B
100 pF
Byte or Page mode
25°C, Vcc = 5.0V, Block
mode
Not 100% tested. C
B
= Total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
2003 Microchip Technology Inc.
DS21160F-page 3