24AA32A/24LC32A
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24XX32A supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
serial clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 24XX32A
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device deter-
mines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically
unlimited, (although only the last thirty two bytes will be
stored when doing a write operation). When an over-
write does occur it will replace data in a first-in first-out
(FIFO) fashion.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX32A does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All com-
mands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
The device that acknowledges, has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX32A) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 3-1:
(A)
SCL
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
(C)
(A)
SDA
START
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
STOP
CONDITION
2003 Microchip Technology Inc.
DS21713D-page 5
MICROCHIP [ MICROCHIP TECHNOLOGY ]
