93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
3.0
PIN DESCRIPTIONS
PIN DESCRIPTIONS
SOIC/PDIP/
MSOP/TSSOP/
DFN
1
2
3
4
5
6
7
8
SOT-23
5
4
3
1
2
N/A
N/A
6
Rotated SOIC
3
4
5
6
7
8
1
2
Chip Select
Serial Clock
Data In
Data Out
Ground
Organization / 93XX66C
No Internal Connection / 93XX66A/B
No Internal Connection
Power Supply
Function
TABLE 3-1:
Name
CS
CLK
DI
DO
V
SS
ORG/NC
NC
V
CC
3.1
Chip Select (CS)
A high level selects the device; a low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
data bits before an instruction is executed. CLK and DI
then become “don’t care” inputs waiting for a new Start
condition to be detected.
3.3
Data In (DI)
Data In (DI) is used to clock in a Start bit, opcode,
address and data synchronously with the CLK input.
3.4
Data Out (DO)
3.2
Serial Clock (CLK)
Data Out (DO) is used in the Read mode to output data
synchronously with the CLK input (T
PD
after the posi-
tive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum Chip Select Low Time
(T
CSL
) and an erase or write operation has been
initiated.
The Status signal is not available on DO, if CS is held
low during the entire erase or write cycle. In this case,
DO is in the High-Z mode. If status is checked after the
erase/write cycle, the data line will be high to indicate
the device is ready.
Note:
Issuing a Start bit and then taking CS low
will clear the Ready/Busy status from DO.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93XX series
device. Opcodes, address and data bits are clocked in
on the positive edge of CLK. Data bits are also clocked
out on the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to Clock High Time (T
CKH
) and
Clock Low Time (T
CKL
). This gives the controlling
master freedom in preparing opcode, address and
data.
CLK is a “don’t care” if CS is low (device deselected). If
CS is high, but the Start condition has not been
detected (DI =
0),
any number of clock cycles can be
received by the device without changing its status (i.e.,
waiting for a Start condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
3.5
Organization (ORG)
When the ORG pin is connected to V
CC
or Logic HI, the
(x16) memory organization is selected. When the ORG
pin is tied to V
SS
or Logic LO, the (x8) memory
organization is selected. For proper operation, ORG
must be tied to a valid logic level.
93XX66A devices are always x8 organization and
93XX66B devices are always x16 organization.
DS21795C-page 12
©
2005 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
