PIC18F2480/2580/4480/4580
FIGURE 28-20:
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
Pin
RC7/RX/DT
Pin
120
121
121
122
TABLE 28-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
120
Symbol
Characteristic
Min
Max
Units
Conditions
T
CK
H2
DT
V SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid
T
CKRF
T
DTRF
Clock Out Rise Time and Fall Time
(Master mode)
Data Out Rise Time and Fall Time
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
—
—
—
—
—
—
40
100
20
50
20
50
ns
ns
ns
ns
ns
ns
V
DD
= 2.0V
V
DD
= 2.0V
V
DD
= 2.0V
121
122
FIGURE 28-21:
RC6/TX/CK
Pin
RC7/RX/DT
Pin
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126
Note:
Refer to Figure 28-4 for load conditions.
TABLE 28-23: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param.
No.
125
126
Symbol
Characteristic
Min
10
15
Max
—
—
Units
ns
ns
Conditions
T
DT
V2
CKL
SYNC RCV (MASTER & SLAVE)
Data Hold before CK
↓
(DT hold time)
T
CK
L2
DTL
Data Hold after CK
↓
(DT hold time)
©
2009 Microchip Technology Inc.
DS39637D-page 455
MICROCHIP [ MICROCHIP TECHNOLOGY ]
