PIC18F2480/2580/4480/4580
FIGURE 28-22:
A/D CONVERSION TIMING
BSF ADCON0, GO
(Note 2)
Q4
A/D CLK
132
131
130
A/D DATA
9
8
7
...
...
2
1
0
ADRES
ADIF
GO
OLD_DATA
NEW_DATA
T
CY
DONE
SAMPLE
Note
1:
2:
SAMPLING STOPPED
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the
SLEEP
instruction
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 28-25: A/D CONVERSION REQUIREMENTS
Param
Symbol
No.
130
T
AD
Characteristic
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
PIC18FXXXX
PIC18LFXXXX
131
132
135
136
T
CNV
T
ACQ
T
SWC
T
AMP
Conversion Time
(not including acquisition time)
(Note 2)
Acquisition Time
(Note 3)
Switching Time from Convert
→
Sample
Amplifier Settling Time
(Note 5)
Min
0.7
1.4
—
—
11
1.4
—
1
Max
25.0
(1)
25.0
1
3
12
—
(Note 4)
—
(1)
Units
μs
μs
μs
μs
T
AD
μs
—
μs
Conditions
T
OSC
based, V
REF
≥
3.0V
V
DD
= 2.0V;
T
OSC
based, V
REF
full range
A/D RC mode
V
DD
= 2.0V;
A/D RC mode
-40°C to +85°C
This may be used if the “new” input
voltage has not changed by more
than 1 LSb (i.e., 5 mV @ 5.12V)
from the last sampled voltage (as
stated on C
HOLD
).
Note 1:
2:
3:
4:
5:
The time of the A/D clock period is dependent on the device frequency and the T
AD
clock divider.
ADRES register may be read on the following T
CY
cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
DD
to AV
SS
or AV
SS
to AV
DD
). The source impedance (R
S
) on the input channels is
50Ω.
On the following cycle of the device clock.
See
for minimum conditions when input
voltage has changed more than 1 LSb.
©
2009 Microchip Technology Inc.
DS39637D-page 457
MICROCHIP [ MICROCHIP TECHNOLOGY ]
