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PIC18F4580-I/PT 参数 Datasheet PDF下载

PIC18F4580-I/PT图片预览
型号: PIC18F4580-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器与ECAN技术, 10位A / D和纳瓦技术 [28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路时钟
文件页数/大小: 490 页 / 8912 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2480/2580/4480/4580  
18.3.3  
ENABLING SPI I/O  
18.3.4  
TYPICAL CONNECTION  
To enable the serial port, MSSP Enable bit, SSPEN  
(SSPCON1<5>), must be set. To reset or reconfigure  
SPI mode, clear the SSPEN bit, reinitialize the  
SSPCON registers and then set the SSPEN bit. This  
configures the SDI, SDO, SCK and SS pins as serial  
port pins. For the pins to behave as the serial port func-  
tion, some must have their data direction bits (in the  
TRIS register) appropriately programmed as follows:  
Figure 18-2 shows a typical connection between two  
microcontrollers. The master controller (Processor 1)  
initiates the data transfer by sending the SCK signal.  
Data is shifted out of both shift registers on their pro-  
grammed clock edge and latched on the opposite edge  
of the clock. Both processors should be programmed to  
the same Clock Polarity (CKP), then both controllers  
would send and receive data at the same time.  
Whether the data is meaningful (or dummy data)  
depends on the application software. This leads to  
three scenarios for data transmission:  
• SDI is automatically controlled by the SPI module  
• SDO must have TRISC<5> bit cleared  
• SCK (Master mode) must have TRISC<3> bit  
cleared  
• Master sends data – Slave sends dummy data  
• Master sends data – Slave sends data  
• SCK (Slave mode) must have TRISC<3> bit set  
• SS must have TRISF<7> bit set  
• Master sends dummy data – Slave sends data  
Note:  
When the module is enabled and in  
Master mode (CKE, SSPSTAT<6> = 1), a  
small glitch of approximately half a TCY  
may be seen on the SCK pin. To resolve  
this, keep the SCK pin as an input while  
setting SPEN. Then, configure the SCK  
pin as an output (TRISC<3> = 0).  
Any serial port function that is not desired may be  
overridden by programming the corresponding Data  
Direction (TRIS) register to the opposite value.  
FIGURE 18-2:  
SPI MASTER/SLAVE CONNECTION  
SPI Master SSPM<3:0> = 00xxb  
SPI Slave SSPM<3:0> = 010xb  
SDO  
SDI  
Serial Input Buffer  
(SSPBUF)  
Serial Input Buffer  
(SSPBUF)  
SDI  
SDO  
SCK  
Shift Register  
(SSPSR)  
Shift Register  
(SSPSR)  
LSb  
MSb  
MSb  
LSb  
Serial Clock  
SCK  
PROCESSOR 1  
PROCESSOR 2  
© 2009 Microchip Technology Inc.  
DS39637D-page 195