TC500/A/510/514
4.0
4.1
DETAILED DESCRIPTION
Dual Slope Conversion Principles
Actual data conversion is accomplished in two
phases: input signal integration and reference voltage
de-integration.
The integrator output is initialized to 0V prior to the start
of integration. During integration, analog switch S
1
connects V
IN
to the integrator input where it is
maintained for a fixed time period (T
INT
). The
application of V
IN
causes the integrator output to depart
0V at a rate determined by the
magnitude
of V
IN
and a
direction determined by the
polarity
of V
IN
. The de-
integration phase is initiated immediately at the
expiration of T
INT
.
During de-integration, S1 connects a reference voltage
(having a polarity opposite that of V
IN
) to the integrator
input. At the same time, an external precision timer is
started. The de-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The de-
integration time period (T
DEINT
), as measured by the
precision timer, is directly proportional to the magnitude
of the applied input voltage (see
A simple mathematical equation relates the input
signal, reference voltage and integration time:
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate.
Interference signals with frequencies at integral
multiples of the integration period are, theoretically,
completely removed, since the average value of a sine
wave of frequency (1/T) averaged over a period (T) is
zero.
Integrating converters often establish the integration
period to reject 50/60 Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure
Normal mode
rejection is limited in practice to 50 to 65 dB, since the
line frequency can deviate by a few tenths of a percent
Normal Mode Rejection (dB)
30
T = Measurment
Period
20
10
0
0.1/T
1/T
Input Frequency
10/T
EQUATION 4-1:
V
REF
C
DEINT
T
1
-----------------------
∫
INT
V
IN
(
T
)DT
= -------------------------------
-
-
R
INT
C
INT 0
R
INT
C
INT
Where:
V
REF
T
INT
t
DEINT
=
=
=
Reference Voltage
Signal Integration time (fixed)
Reference Voltage Integration time
(variable)
FIGURE 4-1:
Integrating Converter
Normal Mode Rejection.
80
Normal Mode Rejeciton (dB)
70
60
50
40
30
DEV
SIN 60 p t (1 – 100 )
Normal Mode = 20 LOG
60 p t (1 – DEV)
Rejection
100
DEV = Deviation from 60 Hz
t = Integration Period
t = 0.1 sec
For a constant V
IN
:
EQUATION 4-2:
V
IN
T
DEINT
-
=
V
REF
-----------------
T
INT
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
20
0.01
0.1
1.0
Line Frequency Deviation from 60 Hz (%)
FIGURE 4-2:
Line Frequency Deviation.
©
2008 Microchip Technology Inc.
DS21428E-page 9
MICROCHIP [ MICROCHIP TECHNOLOGY ]
