SP8858
DESCRIPTION
Prescaler and Dividers
The block diagram of a dual modulus divider arrangement
is shown in Fig. 5. The N/N11 prescaler, together with the
A and M dividers, divide the RF input frequency down to the
comparison frequency at the phase detector input. The
comparison frequency, F
REF
, sets the resolution of a single
loop synthesiser; when A is incremented (or decremented) by
one, the loop output frequency automatically increments (or
decrements) by F
REF
Hz. When the dividers are reset, at the
end of each count cycle, the modulus of the prescaler is set
to N11 and the input frequency to the A and M dividers is then
RFinput
4(N11)
Hz. The output of the A counter controls the
prescaler modulus, which is set to N when A reaches its
programmed value. The M divider continues to count at the
rate RFinput
4N
until it reaches its programmed value, at
which point the dividers are reset and the count cycle starts
again. The division ratio of this arrangements is therefore
A(N11)
1
(M2A)N = MN1A
It is evident that for this arrangement to work M must
always be programmed greater than or equal to A and A must
be able to count to N21. These restrictions set a minimum
count of N
2
2N;
below this value some division ratios will not
be available.
The SP8858 prescaler can be set to
48/9
or
416/17
mode
by setting the appropriate bit of the reference word. The
A divider is a 4-bit counter, whilst the M divider is a 15-bit
counter. The minimum division ratio, with the 8/9 prescaler, is
8
2
28
= 56, whilst the maximum division ratio, with the 16/17
prescaler, is 16(2
15
21)1(2
4
21)
= 524287.
If the 8/9 prescaler is used the MSB of the A counter must
be programmed to 0 and the maximum RF input frequency
must be reduced to 750MHz.
reference current into pin 24 (RPD). An external
transimpedance amplifier is required to provide the voltage
drive to the VCO. This requirement is usually performed by
the loop filter operational amplifier which is designed to
provide a type II third order control loop.
Data Entry and Control
The SP8858 is programmed using the serial data interface.
Data is entered into the chip on the DATA pin and clocked into
the internal shift register by the positive going edge of the
CLOCK signal with the ENABLE pin held high. While ENABLE
is high, changes to the shift register will not affect the current
count cycle. On the falling edge of ENABLE the data held in
the shift register is transferred to one of the three buffers (F1,
F2 or reference). Fig. 4 shows the timing requirements for
these three signals.
The 2 LSBs of the 24-bit shift register, C1 and C2, determine
which of the three buffers is loaded with the data held in the
remaining 22 bits as shown in Table 2.
2-bit SR contents
C2
0
1
0
1
C1
0
0
1
1
Buffer loaded
F1
F2
Active A (only the A divider of the
active buffer is changed)
Reference
Table 2
If the F1 buffer (C2 = 0, C1 = 0) is selected the 22 MSBs
of the shift register are transferred to it. 19 bits of the buffer
provide the data for the A and M dividers; the three remaining
bits control the charge pump current multiplication factor and
the sense of the phase detector. The F2 buffer performs the
same function so that an alternative divider word and/or
phase detector gain can be stored.
The CP current can be multiplied by up to four times by
programming bits G1 and G2 as shown in Table 3. The
maximum charge pump output current is
62mA.
The reference current can be set by resistor RPD
connected between V
CC
and pin 24 so that:
Ipin 24 = (V
CC
21·5)/RPD
I
OUT
= G3Ipin 24 (G is multiplication factor)
Phase detector gain, K
PD
= I
OUT
/2p A/rad
See Applications, Loop Filter Design
F1 or F2 word
G2
0
1
0
1
G1
0
0
1
1
Charge pump 1
current (
µ
A)
50
75
125
200
Charge pump 2
multiplier
1
1·5
2·5
4
Reference Source and Divider
The reference source for the SP8858 is obtained from an
on-chip oscillator, stabilised by an external quartz crystal. The
oscillator circuit will also function as a buffer amplifier if an
external reference is preferred. In the latter case the signal,
should be AC coupled into pin 20 (see Fig. 12).
The reference oscillator drives a divider stage, the output
of which is the reference signal to the phase comparator. The
PLL controls the input voltage to an external VCO so that the
divided VCO signal is phased locked to this reference signal.
The dynamics of the control loop are determined by the
external loop filter.
The 13-bit reference divider is fully programmable and can
be set to any ratio between 1 and 8191. The programmed
word is stored in the internal reference buffer.
Phase Comparator and Charge Pump
The digital phase detector is sensitive to frequency and
phase errors. The basic circuit for a conventional digital
phase/frequency detector is based on two D type flip-flops.
Initially the flip-flops are reset, each one is then set by the
respective pulses of the M and R divider outputs. When both
flip-flops have been set they are immediately reset. In this way
the output of one flip-flop is a pulse whose width is proportional
to phase difference, whilst the second flip-flop is a narrow
pulse determined by the time to reset. The phase detector
outputs drive a charge pump amplifier. One output controls a
constant current source, the other an identical current sink
connected to the same node (CP output, pin 25). The SP8858
phase/frequency detector has been modified and improved to
provide a linear characteristic, thus eliminating deadband
effects.
The phase detector gain is determined by the output
current from the charge pump (±I
OUT
) which is set by a
Table 3 Charge pump currents
When the SENSE bit is set to 1 the inputs and clocks to the
phase detector flip-flops are reversed. The bit should be set
to 1 for a VCO with a positive frequency v. voltage characteristic.
The sense bit also swaps the outputs FREF and FPD on pins
4 and 5. Fig. 1 shows the pin-out for SENSE = 0.
The active buffer, i.e. the one that is currently used to
update the dividers, is selected at pin 13 (F1/F2). A high on
this pin selects F1. The F2 word can be updated while F1 is
6
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