SP8858
q
q
The divider in the feedback path imposes limitations on the
designer because it reduces the DC gain of the loop and
also because it unavoidably introduces a measurement
error. The contribution to
f
o(s) phase noise power of the
f
i(s) signal, at frequency offsets within the loop bandwidth,
is multiplied by N
2
(i.e. increases by 20logN dB); this may
impose a specific loop bandwidth for optimum phase
noise.
Physical imperfections in the charge pump and active loop
filter circuits force periodic corrections (at the rate of
1/F
REF
) when the loop is phase-locked. The resulting
disturbance frequency modulates the VCO producing
reference sidebands in the output signal spectrum. The
closed-loop bandwidth must be much less than F
REF
for
reasonable sideband suppression.
individual application and to ensure that the minimum voltage
swing at the RF input is within the guaranteed operating range
over the full tuning range of the application. The SP8858
incorporates a pre-amplifier at the RF input and the dividers
can be seen to operate well below the guaranteed operating
range. Fig. 9 shows a typical sensitivity curve as measured on
the demonstration board board driven by a 50Ω signal
generator (sensitivity is the lowest power level at which the
divider operates without mis-counting). The dividers could be
more susceptible to spurious interference at low drive levels
causing the dividers to mis-count. However, driving the RF
input with relatively high levels will ensure greater immunity
from interference signals.
j1
j
0.5
j2
The design of the filter F(s), suitable for any given
application, may require careful trade-offs between the
requirement to meet the phase noise and the spurious output
specification and the settling time specification:
Example 1
In applications where high resolution is required
(the resolution is F
REF
Hz) the imposed closed loop bandwidth
(less than F
REF
Hz) could result in an unacceptably long time
to acquire phase lock.
Example 2
If a relatively high feedback division ratio is
required the 20logN increase in reference phase noise power,
seen at the output, could also impose a relatively narrow
closed loop bandwidth and hence a long acquisition time.
The roots of the characteristic equation in the closed loop
transfer function,
f
o(s)/
f
i(s), are manipulated through
changes to the DC loop gain and the selection of the pole(s)
and zero(s) in F(s). Careful mathematical analysis is a
prerequisite to successful PLL synthesiser design. If the
analysis shows that the simple PLL as shown in Fig.12 is not
suitable then there are numerous modifications that can be
made to the basic loop and the texts listed in the References
should be consulted for more information.
The Mitel Application Note AN194 (Ref. 9) provides specific
guidance on noise minimisation and loop filter design for the
SP8858 user. The section Loop Filter Design below gives
details of the formula that can be used to implement the loop-
filter given that the desired second order characteristics are
known, i.e. the desired natural loop frequency
v
n
and damping
factor
z
.
j
0.2
j5
0
0.2
0.5
1
2
5
2
j
5
2
j
0.2
2
j
0.5
2
j
1
2
j
2
NORMALISED TO 50Ω
START 102MHz, STOP 2000MHz
Fig. 8 Demonstration board input impedance
0
25
210
215
220
225
230
235
50
100
500
1000
1500
2000
2300
DESIGN IMPLEMENTATION
RF inputs
The availability of a suitable VCO should be considered
early in a project because information on the tuning range, the
tuning gain in Hz/V and the output noise spectrum is required
for the initial mathematical analysis. Variation in the tuning
gain over the tuning range should be minimised as this
parameter feeds into the closed loop characteristic equation.
There is also a trade-off between the requirement for a high
tuning gain (which requires the use of a relatively low Q
resonator) and phase noise.
The VCO, whether bought in or designed for the application,
must also be able to simultaneously drive the SP8858 RF input
as well as the input of the next stage in the system. A power
splitter and active buffer may be required in some applications.
The example in Fig.12 includes a simple resistive power
splitter. This type of buffer introduces a 6dB loss but is
adequate if the VCO output power is sufficient and if the
intention is simply to assess the SP8858 by monitoring the
output signal using a 50Ω measurement system.
The SP8858’s RF input frequency specification covers the
range 80MHz to 1·5GHz and the input impedance varies with
frequency; a typical Smith chart is shown in Fig. 8. It is
advisable to consider transmission line effects for each
RF INPUT FREQUENCY (MHz)
Fig. 9 Typical sensitivity for demo. board at 25°C
Reference Input
When the loop is phase-locked the output signal, Qo(s),
takes on the long term stability characteristics of the reference
signal. In many applications a crystal stabilised oscillator is
adequate as the reference source Qi(s). The VCO output
signal is divided down and compared with the reference
9
MITEL [ MITEL NETWORKS CORPORATION ]
