3820 (MITSUBISHI) PDF技术资料下载 3820 供应信息 IC Datasheet 数据表 (8/66 页)-芯三七

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL DESCRIPTION

Central Processing Unit (CPU)

The 3820 group uses the standard 740 family instruction set. Re-

fer to the table of 740 family addressing modes and machine in-

structions or the SERIES 740 <Software> User’s Manual for de-

tails on the instruction set.

Machine-resident 740 family instructions are as follows:

The FST and SLW instruction cannot be used.

The STP, WIT, MUL, and DIV instruction can be used.

CPU Mode Register

The CPU mode register is allocated at address 003B16.

The CPU mode register contains the stack page selection bit and

the internal system clock selection bit.

7

0

CPU mode register

(

CPUM (CM) : address 003B16)

Processor mode bits

b1 b0

0

1

0

1

0

1

: Single-chip mode

:

Not available

Stack page selection bit

0

1

: 0 RAM in the zero page is used as stack area

: 1 RAM in page 1 is used as stack area

Not used (returns “1” when read)

(Do not write “0” to this bit)

Port XC switch bit

0

1

: I/O port

: XCIN, XCOUT

Main clock ( XIN–XOUT) stop bit

0

1

: Oscillating

: Stopped

Main clock division ratio selection bit

0

1

: f(XIN)/2 (high-speed mode)

: f(XIN)/8 (middle-speed mode)

Internal system clock selection bit

0

1

: XIN-XOUT selected (middle-/high-speed mode)

: XCIN-XCOUT selected (low-speed mode)

Fig. 1 Structure of CPU mode register

10

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MEMORY

Zero Page

Special Function Register (SFR) Area

The Special Function Register area in the zero page contains con-

trol registers such as I/O ports and timers.

The 256 bytes from addresses 000016 to 00FF16 are called the

zero page area. The internal RAM and the special function regis-

ters (SFR) are allocated to this area.

The zero page addressing mode can be used to specify memory

and register addresses in the zero page area. Access to this area

with only 2 bytes is possible in the zero page addressing mode.

RAM

RAM is used for data storage and for stack area of subroutine

calls and interrupts.

Special Page

ROM

The 256 bytes from addresses FF0016 to FFFF16 are called the

special page area. The special page addressing mode can be

used to specify memory addresses in the special page area. Ac-

cess to this area with only 2 bytes is possible in the special page

addressing mode.

The first 128 bytes and the last 2 bytes of ROM are reserved for

device testing and the rest is user area for storing programs.

Interrupt Vector Area

The interrupt vector area contains reset and interrupt vectors.

RAM area

Address

XXXX16

RAM size

(bytes)

000016

SFR area

192

256

384

512

640

768

896

1024

00FF16

013F16

01BF16

023F16

02BF16

033F16

03BF16

043F16

Zero page

004016

LCD display RAM area

005416

010016

RAM

XXXX¹⁶

Reserved area

Not used

044016

ROM area

Address

YYYY16

Address

ZZZZ16

ROM size

(bytes)

YYYY16

Reserved ROM area

(128 bytes)

4096

8192

F000¹⁶

E00016

D00016

C00016

B00016

A00016

900016

800016

F08016

E08016

D08016

C08016

B08016

A08016

908016

808016

12288

16384

20480

24576

28672

32768

ZZZZ16

ROM

FF0016

FFDC16

Special page

Interrupt vector area

Reserved ROM area

FFFE16

FFFF16

Fig. 2 Memory map diagram

11

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Port P0 (P0)

Timer X (low-order) (TXL)

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Port P0 direction register (P0D)

Port P1 (P1)

Timer X (high-order) (TXH)

Timer Y (low-order) (TYL)

Timer Y (high-order) (TYH)

Timer 1 (T1)

Port P1 direction register (P1D)

Port P2 (P2)

Port P2 direction register (P2D)

Port P3 (P3)

Timer 2 (T2)

Timer 3 (T3)

Timer X mode register (TXM)

Timer Y mode register (TYM)

Timer 123 mode register (T123M)

φ output control register (CKOUT)

Port P4 (P4)

Port P4 direction register (P4D)

Port P5 (P5)

Port P5 direction register (P5D)

Port P6 (P6)

Port P6 direction register (P6D)

Port P7 (P7)

Port P7 direction register (P7D)

PULL register A (PULLA)

PULL register B (PULLB)

Watchdog timer control register (WDTCON)

Segment output enable register (SEG)

LCD mode register (LM)

Transmit/Receive buffer register (TB/RB)

Serial I/O1 status register (SIO1STS)

Serial I/O1 control register (SIO1CON)

UART control register (UARTCON)

Baud rate generator (BRG)

Interrupt edge selection register (INTEDGE)

CPU mode register (CPUM)

Interrupt request register 1(IREQ1)

Interrupt request register 2(IREQ2)

Interrupt control register 1(ICON1)

Interrupt control register 2(ICON2)

Serial I/O2 control register (SIO2CON)

Serial I/O2 register (SIO2)

Fig.3 Memory map of special function register (SFR)

12

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O PORTS

7

0

PULL register A

(PULLA : address 0016 16

Direction Registers (ports P2, P41–P47, and

P5–P7)

)

P0

P1

P2

P3

P7

0

–P0

–P1

–P2

–P3

, P7

7

1

pull-down

pull-up

The 3820 group has 43 programmable I/O pins arranged in seven

I/O ports (ports P0–P2 and P4–P7). The I/O ports P2, P41–P47,

and P5–P7 have direction registers which determine the input/out-

put direction of each individual pin. Each bit in a direction register

corresponds to one pin, each pin can be set to be input port or

output port.

pull-down

pull-up

Not used (return "0" when read)

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

7

0

PULL register B

(PULLB : address 0017 16

)

P4

P5

P6

1

4

0

4

0

–P4

–P5

, P6

3

7

3

7

1

pull-up

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are

floating. If a pin set to input is written to, only the port output latch

is written to and the pin remains floating.

Not used (return "0" when read)

0 : Disable

1 : Enable

Direction Registers (ports P0 and P1)

Ports P0 and P1 have direction registers which determine the in-

put /output direction of each individual port.

Note : The contents of PULL register A

and PULL register B do not affect

Each port in a direction register corresponds to one port, each

port can be set to be input or output.

ports programmed as the output ports.

Fig. 4 Structure of PULL register A and PULL register B

When “0” is written to the bit 0 of a direction register, that port be-

comes an input port. When “1” is written to that port, that port be-

comes an output port.

Bits 1 to 7 of ports P0 and P1 direction registers are not used.

Ports P3 and P40

These ports are only for input.

Pull-up/Pull-down Control

By setting the PULL register A (address 001616) or the PULL reg-

ister B (address 001716), ports except for port P40 can control ei-

ther pull-down or pull-up (pins that are shared with the segment

output pins for LCD are pull-down; all other pins are pull-up) with a

program.

However, the contents of PULL register A and PULL register B do

not affect ports programmed as the output ports.

13

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Name

Input/Output

I/O Format

CMOS compatible

input level

Non-Port Function

Related SFRs

PULL register A

Segment output

enable register

PULL register A

Segment output

enable register

PULL register A

Interrupt control

register 2

Diagram No.

P00/SEG24–

P07/SEG31

Input/output,

individual ports

Port P0

LCD segment output

CMOS 3-state output

CMOS compatible

input level

(1)

P10/SEG32–

P17/SEG39

Input/output,

individual ports

Port P1

Port P2

Port P3

LCD segment output

CMOS 3-state output

CMOS compatible

input level

Key input(Key-on

wake up) interrupt

input

Input/output,

individual bits

P20 – P27

(2)

CMOS 3-state output

PULL register A

Segment output

enable register

P30/SEG16–

P37/SEG23

CMOS compatible

input level

Input

LCD segment output

(3)

(4)

(5)

CMOS compatible

input level

P40

PULL register B

φ output control

register

P41/ φ

φ clock output

PULL register B

Interrupt edge selection

register

P42/INT0,

P43/INT1

Port P4

CMOS compatible

input level

Input/output,

individual bits

External interrupt input

(2)

CMOS 3-state output

P44/RXD

PULL register B

Serial I/O1 control register

Serial I/O1 status register

UART control register

(6)

(7)

P45/TXD

Serial I/O1 function I/O

Serial I/O2 function I/O

P46/SCLK1

P47/SRDY1

P50/SIN2

(8)

(9)

(10)

(11)

(12)

(13)

PULL register B

Serial I/O2 control

register

P51/SOUT2

P52/SCLK2

P53/SRDY2

PULL register B

P54/CNTR0

P55/CNTR1

P56/TOUT

CMOS compatible

input level

Timer I/O

(14)

(10)

(15)

Input/output,

individual bits

Timer X mode register

PULL register B

Port P5

CMOS 3-state output

Timer I/O

Timer Y mode register

PULL register B

Timer output

Timer 123 mode register

PULL register B

P57/INT2

External interrupt input

Interrupt edge

(2)

selection register

PULL register B

External interrupt input

Real time port

Timer X mode register

Interrupt edge

CMOS compatible

input level

P60/INT3/RTP0

Input/output,

individual bits

function output

(16)

Port P6

Port P7

selection register

PULL register B

CMOS 3-state output

Real time port

function output

P61/RTP1

P70/XCOUT

P71/XCIN

Timer X mode register

CMOS compatible

input level

Sub-clock

generating circuit

I/O

(17)

(18)

Input/output,

individual bits

PULL register A

CPU mode register

CMOS 3-state output

COM

SEG

0

-COM

3

Common

Segment

output

LCD common output

LCD segment output

LCD mode register

(19)

(20)

0

-SEG15

Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

14

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1)Ports P0,P1

(2)Ports P2,P42,P43,P57

V

L2/VL3

Pull-up control

V

L1/VSS

Segment output enable bit

(Note)

Direction register

Data bus

Port latch

Data bus

Port latch

Key input (Key-on wake up) interrupt input

INT –INT interrupt input

0

2

Pull-down control

Segment output enable bit

Note. Bit 0 of port P0 direction register and

port P1 direction register.

(3)Ports P30–P37

(4)Port P4

0

VL2/VL3

Data bus

V

L1/VSS

Data bus

Pull-down control

Segment output enable bit

(6)Port P4

4

(5)Port P4

1

Pull-up control

Serial I/O1 enable bit

Reception enable bit

Direction register

Port latch

Data bus

Port latch

φ output control bit

φ

Serial I/O1 input

(8)Port P4

6

(7)Port P4

5

Serial I/O1 synchronization clock

selection bit

Pull-up control

Serial I/O1 enable bit

P4

5

/T

X

D P-channel output disable bit

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Transmission enable bit

Direction register

Port latch

Data bus

Port latch

Data bus

Serial I/O1 clock output

Serial I/O1 output

Serial I/O1 clock input

Fig. 5 Port block diagram (1)

15

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(9) Port P4

7

(10) Ports P50,P5

5

Pull-up control

Serial I/O1 mode selection bit

Serial I/O1 enable bit

S

RDY1 output enable bit

Direction register

Data bus

Port latch

Data bus

Port latch

Serial I/O2 input

Serial I/O1 ready output

CNTR

1

interrupt input

(11) Port P5

1

(12) Port P5

2

Pull-up control

Internal synchronization clock

select bits

Pull-up control

Serial I/O2 port selection bit

Serial I/O2 transmit completion signal

Serial I/O2 port selection bit

Direction register

Port latch

Data bus

Port latch

Serial I/O2 clock output

Serial I/O2 output

Serial I/O2 clock input

(13) Port P5

3

(14) Port P5

4

Pull-up control

S

RDY2 output enable bit

Direction register

Data bus

Port latch

Data bus

Port latch

Timer X operating mode bit

Serial I/O2 ready output

(Pulse output mode selection)

Timer output

CNTR0 interrupt input

(15) Port P5

6

(16) Ports P60, P61

Pull-up control

Direction register

Data bus

Port latch

T

OUT output control bit

Timer output

Real time port control bit

Data for real time port

INT

3

interrupt input

Except P6

1

Fig. 6 Port block diagram (2)

16

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(17) Port P7

0

(18) Port P71

Port selection/Pull-up control

Port X^Cswitch bit

Direction register

Data bus

Port latch

Data bus

Oscillation circuit

Port P71

Sub-clock generating circuit input

Port XC switch bit

(19) COM

0

–COM3

(20) SEG0 – SEG15

VL2/VL3

The voltage applied to the sources of

P-channel and N-channel transistors

is the controlled voltage by the bias

value.

V^L3

VL1/VSS

VL2

VL1

The gate input signal of each transistor is

controlled by the LCD duty ratio and the

bias value.

VSS

Fig. 7 Port block diagram (3)

17

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

INTERRUPTS

Interrupt Operation

Interrupts occur by sixteen sources: seven external, eight internal,

When an interrupt is received, the contents of the program counter

and processor status register are automatically stored into the

stack. The interrupt disable flag is set to inhibit other interrupts

from interfering.The corresponding interrupt request bit is cleared

and the interrupt jump destination address is read from the vector

table into the program counter.

and one software.

Interrupt Control

Each interrupt is controlled by an interrupt request bit, an interrupt

enable bit, and the interrupt disable flag except for the software in-

terrupt set by the BRK instruction. An interrupt occurs if the corre-

sponding interrupt request and enable bits are “1” and the inter-

rupt disable flag is “0”.

Notes on Use

When the active edge of an external interrupt (INT0–INT3, CNTR0,

or CNTR1) is changed, the corresponding interrupt request bit

may also be set. Therefore, please take following sequence;

(1) Disable the external interrupt which is selected.

(2) Change the active edge selection.

Interrupt enable bits can be set or cleared by software.

Interrupt request bits can be cleared by software, but cannot be

set by software.

The BRK instruction cannot be disabled with any flag or bit. The I

(interrupt disable) flag disables all interrupts except the BRK in-

struction interrupt.

(3) Clear the interrupt request bit which is selected to “0”.

(4) Enable the external interrupt which is selected.

Table 1. Interrupt vector addresses and priority

Interrupt Request

Remarks

Vector Addresses (Note 1)

Interrupt Source

Reset (Note 2)

INT0

Priority

High

Low

Generating Conditions

1

2

FFFD16

FFFC16

At reset

Non-maskable

At detection of either rising or

falling edge of INT0 input

At detection of either rising or

falling edge of INT1 input

At completion of serial I/O1

data reception

External interrupt

FFFB16

FFF916

FFF716

FFFA16

FFF816

FFF616

(active edge selectable)

External interrupt

INT1

3

4

(active edge selectable)

Serial I/O1

receive

Valid when serial I/O1 is selected

At completion of serial I/O1

transmit shift or when transmit

buffer register is empty

Serial I/O1

transmit

5

FFF516

FFF416

Valid when serial I/O1 is selected

Timer X

Timer Y

Timer 2

Timer 3

6

7

8

9

FFF316

FFF116

FFEF16

FFED16

FFF216

FFF016

FFEE16

FFEC16

At timer X underflow

At timer Y underflow

At timer 2 underflow

At timer 3 underflow

At detection of either rising or

falling edge of CNTR0 input

At detection of either rising or

falling edge of CNTR1 input

At timer 1 underflow

External interrupt

CNTR0

10

FFEB16

FFEA16

(active edge selectable)

External interrupt

CNTR1

Timer 1

INT2

11

12

13

FFE916

FFE716

FFE516

FFE816

FFE616

FFE416

(active edge selectable)

At detection of either rising or

falling edge of INT2 input

At detection of either rising or

falling edge of INT3 input

At falling of conjunction of input

level for port P2 (at input mode)

At completion of serial I/O2

data transmission or reception

External interrupt

(active edge selectable)

External interrupt

INT3

14

15

16

17

FFE316

FFE116

FFDF16

FFDD16

FFE216

FFE016

FFDE16

FFDC16

(active edge selectable)

External interrupt

Key input

(Key-on wake up)

(valid when an “L” level is applied)

Serial I/O2

Valid when serial I/O2 is selected

Non-maskable software interrupt

BRK instruction

At BRK instruction execution

Notes 1: Vector addresses contain interrupt jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

18

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupt request bit

Interrupt enable bit

Interrupt disable flag (I)

Interrupt request

BRK instruction

Reset

Fig. 8 Interrupt control

7

0

Interrupt edge selection register

(INTEDGE : address 003A16

)

INT

0

interrupt edge selection bit

1

2

3

0 : Falling edge active

1 : Rising edge active

Not used (return “0” when read)

7

0

7 0

Interrupt request register 2

(IREQ2 : address 003D¹⁶

Interrupt request register 1

)

(IREQ1 : address 003C¹⁶

)

INT

0

interrupt request bit

CNTR

0

interrupt request bit

1

CNTR

1

Serial I/O1 receive interrupt request bit

Serial I/O1 transmit interrupt request bit

Timer X interrupt request bit

Timer 1 interrupt request bit

INT

2

3

interrupt request bit

Timer Y interrupt request bit

Key input interrupt request bit

Serial I/O2 interrupt request bit

Not used (returns “0” when read)

Timer 2 interrupt request bit

Timer 3 interrupt request bit

0 : No interrupt request issued

1 : Interrupt request issued

7

0

Interrupt control register 1

7

0

Interrupt control register 2

(ICON2 : address 003F¹⁶

(ICON1 : address 003E¹⁶

)

CNTR

0

1

interrupt enable bit

INT

0

1

interrupt enable bit

CNTR

Timer 1 interrupt enable bit

Serial I/O1 receive interrupt enable bit

Serial I/O1 transmit interrupt enable bit

Timer X interrupt enable bit

INT

2

3

interrupt enable bit

Key input interrupt enable bit

Serial I/O2 interrupt enable bit

Not used (returns “0” when read)

(Do not write “1” to this bit)

Timer Y interrupt enable bit

Timer 2 interrupt enable bit

Timer 3 interrupt enable bit

0 : Interrupts disabled

1 : Interrupts enabled

Fig. 9 Structure of interrupt-related registers

19

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

An example of using a key input interrupt is shown in Figure 9,

where an interrupt request is generated by pressing one of the

keys consisted as an active-low key matrix which inputs to ports

P20–P23.

Key Input Interrupt (Key-on Wake Up)

A key input interrupt request is generated by applying “L” level to

any pin of port P3 that have been set to input mode. In other

words, it is generated when AND of input level goes from “1” to “0”.

Port PXx

"L" level output

PULL register A

Bit 2 = "1"

Key input interrupt request

Port P2

7

direction register = "1"

✽

✽ ✽

Port P2

latch

7

6

5

4

P2

7

output

Port P2

direction register = "1"

6

Port P2

latch

P2

6

Port P2

direction register = "1"

5

Port P2

latch

P2

5

output

Port P2

direction register = "1"

4

Port P2

latch

P24

Port P2

3

direction register = "0"

Port P2

Input reading circuit

✽

✽ ✽

Port P2

latch

3

P2

3

input

Port P2

2

direction register = "0"

✽ ✽

Port P2

latch

2

P2

2

Port P2

1

direction register = "0"

✽

✽ ✽

Port P2

latch

1

P21

Port P2

0

direction register = "0"

✽ ✽

Port P2

latch

0

P20

✽ P-channel transistor for pull-up

✽ ✽ CMOS output buffer

Fig. 10 Connection example when using key input interrupt and port P2 block diagram

20

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Read and write operation on 16-bit timer must be performed for

both high and low-order bytes. When reading a 16-bit timer, read

the high-order byte first. When writing to a 16-bit timer, write the

low-order byte first. The 16-bit timer cannot perform the correct op-

eration when reading during the write operation, or when writing

during the read operation.

TIMERS

The 3820 group has five timers: timer X, timer Y, timer 1, timer 2,

and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,

timer 2, and timer 3 are 8-bit timers.

All timers are down count timers. When the timer reaches “0016”,

an underflow occurs at the next count pulse and the correspond-

ing timer latch is reloaded into the timer and the count is contin-

ued. When a timer underflows, the interrupt request bit corre-

sponding to that timer is set to “1”.

Real time port

control bit "1"

Data bus

Q

D

P60 data for real time port

P60

Latch

P6

0

direction register

"0"

P6 latch

Real time port ⁰

control bit "1"

Q

D

P61 data for real time port

P6

1

Latch

Real time port

control bit "0"

P6

direction register

f(XIN)/16

"0"

P6 latch

Timer X mode register

write signal

1

"1"

(f(X^CIN)/16 in low-speed mode*)

Timer X stop

control bit

Timer X write

control bit

Timer X operat-

CNTR0 active

edge switch bit

ing mode bit

"00","01","11"

Timer X (low) latch (8) Timer X (high) latch (8)

Timer X

interrupt

request

"0"

P54/CNTR0

Timer X (high) (8)

Timer X (low) (8)

"10"

"1"

Pulse width

CNTR

0

measurement

interrupt

request

CNTR

0

active

Pulse output mode

mode

edge switch bit

"0"

"1"

S

Q

Timer Y operating mode bit

"00","01","10"

T

CNTR

1

P54 direction register

Pulse width HL continuously measurement mode

interrupt

request

P54 latch

"11"

Rising edge detection

Falling edge detection

Pulse output mode

f(X^IN)/16

Period

measurement mode

(f(X^CIN)/16 in low-speed mode*)

Timer Y stop

control bit

CNTR1 active

edge switch bit

Timer Y (low) latch (8) Timer Y (high) latch (8)

"00","01","11"

Timer Y

interrupt

request

"0"

P55/CNTR1

Timer Y (low) (8)

Timer Y (high) (8)

"10"Timer Y operating

mode bit

"1"

f(XIN)/16

(f(X^CIN)/16 in low-speed mode*)

Timer 1

interrupt

request

Timer 2 write

control bit

Timer 2 count source

selection bit

Timer 1 count source

selection bit

"0"

Timer 2 latch (8)

Timer 1 latch (8)

Timer 1 (8)

"0"

Timer 2

interrupt

request

Timer 2 (8)

X

CIN

"1"

f(XIN)/16

(f(XCIN)/16 in low-speed mode*)

T

OUT output

T

OUT output

control bit

active edge

switch bit "0"

S

Q

P56/TOUT

T

"1"

P56 latch

Timer 3 latch (8)

"0"

P56

direction register

Timer 3

interrupt

request

T

OUT output control bit

f(XIN)/16(f(XCIN)/16 in low-speed mode*)

Timer 3 (8)

"1"

Timer 3 count

source selection

bit

* Internal clock φ = XCIN/2.

Fig. 11 Timer block diagram

21

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer X

Note on CNTR0 Interrupt Active Edge Selec-

Timer X is a 16-bit timer that can be selected in one of four modes

and can be controlled the timer X write and the real time port by

setting the timer X mode register.

tion

CNTR0 interrupt active edge depends on the CNTR0 active edge

switch bit.

Timer mode

Real Time Port Control

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

While the real time port function is valid, data for the real time port

are output from ports P60 and P61 each time the timer X

underflows. (However, after rewriting a data for real time port, if the

real time port control bit is changed from “0” to “1”, data is output

without the timer X.) If the data for the real time port is changed

while the real time port function is valid, the changed data are out-

put at the next underflow of timer X.

Pulse output mode

Each time the timer underflows, a signal output from the CNTR0

pin is inverted. Except for this, the operation in pulse output mode

is the same as in timer mode. When using a timer in this mode, set

the corresponding port P54 direction register to output mode.

Before using this function, set the corresponding port direction

registers to output mode.

Event counter mode

The timer counts signals input through the CNTR0 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P54 direction register to input mode.

7

0

Timer X mode register

(TXM : address 0027¹⁶)

Pulse width measurement mode

The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode. If

CNTR0 active edge switch bit is “0”, the timer counts while the in-

put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while

the input signal of CNTR0 pin is at “L”. When using a timer in this

mode, set the corresponding port P54 direction register to input

mode.

Timer X write control bit

0 : Write value in latch and counter

1 : Write value in latch only

Real time port control bit

0 : Real time port function invalid

1 : Real time port function valid

P6⁰data for real time port

0 : "L" level output

1 : "H" level output

P6¹data for real time port

0 : "L" level output

1 : "H" level output

Timer X operating mode bits

b5 b4

Timer X Write Control

If the timer X write control bit is “0”, when the value is written in the

address of timer X, the value is loaded in the timer X and the latch

at the same time.

0 0 : Timer mode

If the timer X write control bit is “1”, when the value is written in the

address of timer X, the value is loaded only in the latch. The value

in the latch is loaded in timer X after timer X underflows.

If the value is written in latch only, unexpected value may be set in

the high-order counter when the writing in high-order latch and the

underflow of timer X are performed at the same timing.

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement mode

CNTR⁰active edge switch bit

• CNTR⁰interrupt

0 : Falling edge active

1 : Rising edge active

• Pulse output mode

0 : Start at initial level "H" output

1 : Start at initial level "L" output

• Event counter mode

0 : Rising edge active

1 : Falling edge active

• Pulse width measurement mode

0 : Measure "H" level width

1 : Measure "L" level width

Timer X stop control bit

0 : Count start

1 : Count stop

Fig. 12 Structure of timer X mode register

22

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer Y

Timer Y is a 16-bit timer that can be selected in one of four modes.

7

0

Timer Y mode register

(TYM : address 0028¹⁶

Timer mode

)

The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).

Not used (return "0" when read)

Timer Y operating mode bits

b5 b4

Period measurement mode

0 0 : Timer mode

CNTR1 interrupt request is generated at rising/falling edge of

CNTR1 pin input signal. Simultaneously, the value in timer Y latch

is reloaded in timer Y and timer Y continues counting down. /Ex-

cept for the above-mentioned, the operation in period measure-

ment mode is the same as in timer mode.

0 1 : Period measurement mode

1 0 : Event counter mode

1 1 : Pulse width HL continuously

measurement mode

CNTR

• CNTR

1

active edge switch bit

interrupt

1

The timer value just before the reloading at rising/falling of CNTR1

pin input signal is retained until the timer Y is read once after the

reload.

0 : Falling edge active

1 : Rising edge active

• Period measurement mode

0 : Measure falling edge to falling edge

1 : Measure rising edge to rising edge

• Event counter mode

The rising/falling timing of CNTR1 pin input signal is found by

CNTR1 interrupt. When using a timer in this mode, set the corre-

sponding port P55 direction register to input mode.

0 : Rising edge active

1 : Falling edge active

Timer Y stop control bit

0 : Count start

1 : Count stop

Event counter mode

The timer counts signals input through the CNTR1 pin.

Except for this, the operation in event counter mode is the same

as in timer mode. When using a timer in this mode, set the corre-

sponding port P55 direction register to input mode.

Fig. 13 Structure of timer Y mode register

Pulse width HL continuously measurement mode

CNTR1 interrupt request is generated at both rising and falling

edges of CNTR1 pin input signal. Except for this, the operation in

pulse width HL continuously measurement mode is the same as in

period measurement mode. When using a timer in this mode, set

the corresponding port P55 direction register to input mode.

Note on CNTR1 Interrupt Active Edge Selec-

tion

CNTR1 interrupt active edge depends on the CNTR1 active edge

switch bit. However, in pulse width HL continuously measurement

mode, CNTR1 interrupt request is generated at both rising and

falling edges of CNTR1 pin input signal regardless of the setting of

CNTR1 active edge switch bit.

23

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timer 1, Timer 2, Timer 3

7

0

Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for

each timer can be selected by timer 123 mode register. The timer

latch value is not affected by a change of the count source. How-

ever, because changing the count source may cause an inadvert-

ent count down of the timer. Therefore, rewrite the value of timer

whenever the count source is changed.

Timer 123 mode register

(T123M :address 0029¹⁶)

TOUT output active edge switch bit

0 : Start at "H" output

1 : Start at "L" output

T^OUToutput control bit

0 : T^OUToutput disabled

1 : T^OUToutput enabled

Timer 2 write control bit

0 : Write value in latch and counter

1 : Write value in latch only

Timer 2 count source selection bit

0 : Timer 1 underflow

1 : f(X^IN)/16

(Middle-/high-speed mode)

f(X^CIN)/16

(Low-speed mode)(Note)

Timer 3 count source selection bit

0 : Timer 1 underflow

1 : f(X^IN)/16

Timer 2 Write Control

If the timer 2 write control bit is “0”, when the value is written in the

address of timer 2, the value is loaded in the timer 2 and the latch

at the same time.

If the timer 2 write control bit is “1”, when the value is written in the

address of timer 2, the value is loaded only in the latch. The value

in the latch is loaded in timer 2 after timer 2 underflows.

(Middle-/high-speed mode)

f(X^CIN)/16

(Low-speed mode)(Note)

Timer 1 count source selection bit

0 : f(X^IN)/16

(Middle-/high-speed mode)

f(X^CIN)/16

(Low-speed mode)(Note)

1 : f(X^CIN)

Timer 2 Output Control

When the timer 2 (TOUT) is output enabled, an inversion signal

from pin TOUT is output each time timer 2 underflows.

In this case, set the port P56 shared with the port TOUT to the out-

put mode.

Not used (return "0" when read)

Note : Internal clock φ is f (XCIN)/2 in the low-speed mode.

Note on Timer 1 to Timer 3

When the count source of timer 1 to 3 is changed, the timer count-

ing value may be changed large because a thin pulse is generated

in count input of timer. If timer 1 output is selected as the count

source of timer 2 or timer 3, when timer 1 is written, the counting

value of timer 2 or timer 3 may be changed large because a thin

pulse is generated in timer 1 output.

Fig. 14 Structure of timer 123 mode register

Therefore, set the value of timer in the order of timer 1, timer 2 and

timer 3 after the count source selection of timer 1 to 3.

24

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O1

Clock Synchronous Serial I/O1 Mode

Serial I/O1 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O1. A dedicated timer (baud rate generator)

is also provided for baud rate generation.

Clock synchronous serial I/O1 mode can be selected by setting

the mode selection bit of the serial I/O1 control register to “1”.

For clock synchronous serial I/O1, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB (address 001816).

Data bus

Serial I/O1 control register

Address 001A¹⁶

Address 001816

Receive buffer register (RB)

Receive buffer full flag (RBF)

Receive shift register

Serial I/O receive interrupt request (RI)

P44/RXD

Shift clock

Clock control circuit

P46/SCLK1

Serial I/O1 synchronization

clock selection bit

Frequency division ratio 1/(n+1)

BRG count source selection bit

1/4

f(XIN

)

X

IN

Baud rate generator

Address 001C¹⁶

1/4

Clock control circuit

P47/SRDY1

Falling-edge detector

F/F

Shift clock

Transmit shift register shift completion flag (TSC)

Transmit interrupt source selection bit

P45/TXD

Transmit shift register

Transmit buffer register (TB)

Serial I/O transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Serial I/O1 status register

Address 0019¹⁶

Address 0018¹⁶

Data bus

Fig. 15 Block diagram of clock synchronous serial I/O1

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD

Serial input RxD

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

Receive enable signal SRDY1

Write signal to receive/transmit

buffer register (address 001816

)

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Overrun error (OE)

detection

Notes 1 : The serial I/O1 transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)

or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O1 control register.

2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is

output continuously from the TxD pin.

3 : The serial I/O1 receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Fig. 16 Operation of clock synchronous serial I/O1 function

25

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ter, but the two buffers have the same address in memory. Since

the shift register cannot be written to or read from directly, transmit

data is written to the transmit buffer register, and receive data is

read from the receive buffer register.

Asynchronous Serial I/O1 (UART) Mode

Clock asynchronous serial I/O1 mode (UART) can be selected by

clearing the serial I/O1 mode selection bit of the serial I/O1 control

register to “0”.

The transmit buffer register can also hold the next data to be

transmitted, and the receive buffer register can hold a character

while the next character is being received.

Eight serial data transfer formats can be selected, and the transfer

formats used by a transmitter and receiver must be identical.

The transmit and receive shift registers each have a buffer regis-

Data bus

Address 001816

Receive buffer register(RB)

Character length selection bit

Serial I/O1 control register Address 001A¹⁶

Receive buffer full flag (RBF)

Serial I/O receive interrupt request (RI)

OE

P4⁴/RXD

STdetector

7 bits

8 bits

Receive shift register

1/16

UART control register

Address 001B¹⁶

PE FE SP detector

Clock control circuit

Serial I/O1 synchronization clock selection bit

P4⁶/SCLK1

f(XIN)

Frequency division ratio 1/(n+1)

BRG count source selection bit

1/4

Baud rate generator

Address 001C¹⁶

ST/SP/PA generator

1/16

Transmit shift register shift completion flag (TSC)

Transmit interrupt source selection bit

P4⁵/TXD

Transmit shift register

Serial I/O1 status register

Character length selection bit

Transmit buffer empty flag (TBE)

Transmit buffer register(TB)

Address 001816

Address 001916

Serial I/O1 status register

Data bus

Fig. 17 Block diagram of UART serial I/O1

Transmit or receive clock

Transmit buffer register

write signal

TBE=0

TSC=0

TBE=1

TBE=0

TSC=1^✽

SP

TBE=1

Serial output TXD

ST

D0

D1

ST

D0

D1

SP

^✽Generated at 2nd bit in 2-stop-bit mode

1 start bit

7 or 8 data bits

1 or 0 parity bit

1 or 2 stop bit (s)

Receive buffer register

read signal

RBF=0

RBF=1

SP

RBF=1

SP

ST

Serial input RXD

D0

D1

ST

D0

D1

Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).

2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt

source selection bit (TIC) of the serial I/O1 control register.

3: The serial I/O1 receive interrupt (RI) is set when the RBF flag becomes "1".

4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.

Fig. 18 Operation of UART serial I/O1 function

26

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Serial I/O1 Control Register (SIO1CON) 001A16

The serial I/O1 control register contains eight control bits for the

serial I/O1 function.

UART Control Register (UARTCON) 001B16

The UART control register consists of four control bits (bits 0 to 3)

which are valid when asynchronous serial I/O is selected and set

the data format of an data transfer. One bit in this register (bit 4) is

always valid and sets the output structure of the P45/TXD pin.

Serial I/O1 Status Register (SIO1STS) 001916

The read-only serial I/O1 status register consists of seven flags

(bits 0 to 6) which indicate the operating status of the serial I/O

function and various errors.

Three of the flags (bits 4 to 6) are valid only in UART mode.

The receive buffer full flag (bit 1) is cleared to “0” when the receive

buffer is read.

If there is an error, it is detected at the same time that data is

transferred from the receive shift register to the receive buffer reg-

ister, and the receive buffer full flag is set. A write to the serial I/O

status register clears all the error flags OE, PE, FE, and SE (bit 3

to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE

(bit 7 of the Serial I/O Control Register) also clears all the status

flags, including the error flags.

All bits of the serial I/O1 status register are initialized to “0” at re-

set, but if the transmit enable bit (bit 4) of the serial I/O control reg-

ister has been set to “1”, the transmit shift register shift completion

flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”.

Transmit Buffer/Receive Buffer Register (TB/

RB) 001816

The transmit buffer register and the receive buffer register are lo-

cated at the same address. The transmit buffer register is write-

only and the receive buffer register is read-only. If a character bit

length is 7 bits, the MSB of data stored in the receive buffer regis-

ter is “0”.

Baud Rate Generator (BRG) 001C16

The baud rate generator determines the baud rate for serial trans-

fer.

The baud rate generator divides the frequency of the count source

by 1/(n + 1), where n is the value written to the baud rate genera-

tor.

27

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

0

7

Serial I/O1 status register

Serial I/O1 control register

(SIO1STS : address 0019 ¹⁶

)

(SIO1CON : address 001A 16

BRG count source selection bit (CSS)

0: f(X^IN

)

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

)

1: f(X^IN)/4

Serial I/O1 synchronization clock selection bit (SCS)

•In clock synchronous mode

0 : BRG output/4

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

1 : External clock input

•In UART mode

0 : BRG output/16

1 : External clock input/16

Transmit shift register shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

S

0: P4

1: P4

RDY1 output enable bit (SRDY)

Overrun error flag (OE)

0: No error

1: Overrun error

7

S

RDY1 pin operates as I/O port P4

7

RDY1 pin operates as signal output pin SRDY1

(SRDY1 signal indicates receive enable state)

Parity error flag (PE)

0: No error

1: Parity error

Transmit interrupt source selection bit (TIC)

0: When transmit buffer has emptied

1: When transmit shift operation is completed

Framing error flag (FE)

0: No error

1: Framing error

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Summing error flag (SE)

0: OE U PE U FE =0

1: OE U PE U FE =1

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Not used (returns “1” when read)

Serial I/O1 mode selection bit (SIOM)

0: Clock asynchronous serial I/O1 (UART) mode

1: Clock synchronous serial I/O1 mode

7

0

UART control register

(UARTCON : address 001B ¹⁶

Serial I/O1 enable bit (SIOE)

0: Serial I/O1 disabled

)

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

(pins P4

1: Serial I/O1 enabled

(pins P4 –P4 operate as serial I/O1 pins)

4–P47 operate as I/O pins)

4

7

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

P45/TXD P-channel output disable bit (POFF)

0: CMOS output (in output mode)

1: N-channel open-drain output (in output mode)

Not used (return“1” when read)

Fig. 19 Structure of serial I/O1 control registers

28

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SERIAL I/O2

b7

b0

Serial I/O2 control register

The serial I/O2 function can be used only for clock synchronous

(SIO2CON : address 001D16

)

serial I/O.

Internal synchronization clock select bits

For clock synchronous serial I/O2 the transmitter and the receiver

must use the same clock. If the internal clock is used, transfer is

started by a write signal to the serial I/O2 register.

b2 b1 b0

0 0 0: f(XIN)/8

0 0 1: f(XIN)/16

0 1 0: f(XIN)/32

0 1 1: f(XIN)/64

1 0 0:

1 0 1:

Do not set

Serial I/O2 Control Register (SIO2CON) 001D16

The serial I/O2 control register contains 7 bits which control vari-

ous serial I/O functions.

1 1 0: f(XIN)/128

1 1 1: f(XIN)/256

Serial I/O2 port selection bit

0: I/O port

1: SOUT2,SCLK2 signal output

S

RDY2 output enable bit

0: I/O port

1: SRDY2 signal output

Transfer direction selection bit

0: LSB first

1: MSB first

Synchronization clock selection bit

0: External clock

1: Internal clock

Not used (returns “0” when read)

Fig. 20 Structure of serial I/O2 control register

Internal synchronization

clock select bits

1/8

1/16

Data bus

1/32

X

IN

1/64

1/128

1/256

P53 latch

Synchronization clock

selection bit

"0"

"1"

P5

3

/SRDY2

S

RDY2

Synchronization circuit

"1"

SRDY2 output enable bit

"0"

External clock

P52 latch

"0"

P5

2

1

/SCLK2

/SOUT2

Serial I/O2

interrupt request

Serial I/O counter 2 (3)

"1"

Serial I/O2 port selection bit

P51

latch

"0"

"1"

Serial I/O2 port selection bit

Serial I/O shift register 2 (8)

P50/SIN2

Fig. 21 Block diagram of serial I/O2 function

29

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Transfer clock (Note 1)

Serial I/O2 register

write signal

(Note 2)

Serial I/O2 output

SOUT2

D

2

D

0

D

1

D

3

D

4

D

5

D

6

D7

Serial I/O2 input SIN2

Receive enable signal SRDY2

Serial I/O2 interrupt request bit set

Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial

I/O2 control register.

2: When the internal clock is selected as the transfer clock, the S OUT2 pin goes to high impedance after transfer completion.

Fig. 22 Timing of serial I/O2 function

30

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

the segment output enable register and the LCD display RAM, the

LCD drive control circuit starts reading the display data automati-

cally, performs the bias control and the duty ratio control, and dis-

plays the data on the LCD panel.

LCD DRIVE CONTROL CIRCUIT

The 3820 group has the built-in Liquid Crystal Display (LCD) drive

control circuit consisting of the following.

LCD display RAM

•

Segment output enable register

•

Table 2. Maximum number of display pixels at each

duty ratio

LCD mode register

•

Selector

•

Timing controller

Duty ratio

2

Maximum number of display pixel

80 dots

•

Common driver

•

Segment driver

•

or 8 segment LCD 10 digits

120 dots

Bias control circuit

•

3

4

A maximum of 40 segment output pins and 4 common output pins

can be used.

or 8 segment LCD 15 digits

160 dots

Up to 160 pixels can be controlled for LCD display. When the LCD

enable bit is set to “1” after data is set in the LCD mode register,

or 8 segment LCD 20 digits

7

0

Segment output enable register

(SEG : address 0038¹⁶)

Segment output enable bit 0

0 : Input ports P3⁰–P37

1 : Segment output SEG16–SEG23

Segment output enable bit 1

0 : I/O ports P0⁰, P01

1 : Segment output SEG24,SEG25

Segment output enable bit 2

0 : I/O ports P0²–P07

1 : Segment output SEG26–SEG31

Segment output enable bit 3

0 : I/O ports P1⁰,P11

1 : Segment output SEG32,SEG33

Segment output enable bit 4

0 : I/O port P1²

1 : Segment output SEG34

Segment output enable bit 5

0 : I/O ports P1³–P17

1 : Segment output SEG35–SEG39

Not used (return "0" when read)

(Do not write "1" to this bit)

0

7

LCD mode register

(LM : address 0039¹⁶)

Duty ratio selection bits

0 0 : Not available

0 1 : 2 (use COM⁰,COM1)

1 0 : 3 (use COM⁰–COM2)

1 1 : 4 (use COM⁰–COM3)

Bias control bit

0 : 1/3 bias

1 : 1/2 bias

LCD enable bit

0 : LCD OFF

1 : LCD ON

Not used (returns "0" when read)

(Do not write "1" to this bit)

LCD circuit divider division ratio selection bits

0 0 : LCDCK count source

0 1 : 2 division of LCDCK count source

1 0 : 4 division of LCDCK count source

1 1 : 8 division of LCDCK count source

LCDCK count source selection bit (Note)

0 : f(X^CIN)/32

1 : f(X^IN)/8192

Note : LCDCK is a clock for a LCD timing controller.

Fig. 23 Structure of segment output enable register and LCD mode register

31

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 24 Block diagram of LCD controller/driver

32

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 3. Bias control and applied voltage to VL1–VL3

Bias Control and Applied Voltage to LCD

Power Input Pins

Bias value

Voltage value

To the LCD power input pins (VL1–VL3), apply the voltage shown in

VL3=VLCD

1/3 bias

Table 3 according to the bias value.

VL2=2/3 VLCD

VL1=1/3 VLCD

VL3=VLCD

Select a bias value by the bias control bit (bit 2 of the LCD mode

register).

1/2 bias

VL2=VL1=1/2 VLCD

Common Pin and Duty Ratio Control

The common pins (COM0–COM3) to be used are determined by

duty ratio.

Note 1 : VLCD is the maximum value of supplied voltage for the

LCD panel.

Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the

LCD mode register).

Table 4. Duty ratio control and common pins used

Duty

ratio

Duty ratio selection bit

Common pins used

Bit 1

0

Bit 0

1

2

COM0, COM1 (Note 1)

COM0–COM2 (Note 2)

COM0–COM3

3

4

1

0

1

Notes 1 : COM2 and COM3 are open

2 : COM3 is open

Contrast control

V

L3

V

L3

R1

R4

L2

L1

L2

L1

R2

R3

R5

R4 = R5

R1 = R2 = R3

1/2 bias

1/3 bias

Fig. 25 Example of circuit at each bias

33

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

LCD Display RAM

LCD Drive Timing

Address 004016 to 005316 is the designated RAM for the LCD dis-

play. When “1” are written to these addresses, the corresponding

segments of the LCD display panel are turned on.

The LCDCK timing frequency (LCD drive timing) is generated in-

ternally and the frame frequency can be determined with the fol-

lowing equation;

(frequency of count source for LCDCK)

f(LCDCK)=

(divider division ratio for LCD)

f(LCDCK)

Frame frequency=

duty ratio

Bit

7

6

5

4

3

2

1

0

Address

COM

3

COM

2

COM

1

COM

0

COM

3

COM

2

COM

1

COM0

004016

SEG

0

2

4

6

8

SEG

1

3

5

7

9

004116

004216

004316

004416

004516

004616

SEG10

SEG12

SEG14

SEG16

SEG18

SEG20

SEG22

SEG24

SEG26

SEG28

SEG30

SEG32

SEG34

SEG36

SEG38

SEG11

SEG13

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

SEG15

SEG17

SEG19

SEG21

SEG23

SEG25

SEG27

SEG29

SEG31

SEG33

SEG35

SEG37

SEG39

Fig. 26 LCD display RAM map

34

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Internal logic

LCDCK timing

1/4 duty

Voltage level

VL3

COM0

COM1

COM2

COM3

SEG0

VL2=VL1

VSS

VL3

VSS

OFF

ON

OFF

ON

COM3

COM2

COM1

COM0

COM2

COM1

COM0

1/3 duty

COM⁰

COM1

COM2

VL3

VL2=VL1

VSS

VL3

VSS

SEG0

ON

OFF

ON

OFF

ON

OFF

COM0

COM2

COM1

COM2

COM1

COM0

COM2

1/2 duty

VL3

VL2=VL1

VSS

COM0

COM1

SEG0

VL3

VSS

ON

OFF

ON

OFF

ON

OFF

ON

OFF

COM0

COM1

COM0

COM1

COM0

COM1

COM0

Fig. 27 LCD drive waveform (1/2 bias)

35

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Internal logic

LCDCK timing

1/4 duty

Voltage level

VL3

VL2

VL1

VSS

COM0

COM1

COM2

COM3

SEG0

VL3

VSS

OFF

ON

OFF

ON

COM3

COM2

COM1

COM0

COM2

COM1

COM0

1/3 duty

COM⁰

COM1

COM2

VL3

VL2

VL1

VSS

VL3

SEG0

VSS

ON

OFF

ON

OFF

ON

OFF

COM0

COM2

COM1

COM0

COM2

COM1

COM0

1/2 duty

VL3

VL2

VL1

VSS

COM0

COM1

SEG0

VL3

VSS

ON

OFF

ON

OFF

ON

OFF

ON

OFF

COM1

COM0

COM1

COM0

COM1

COM0

COM1

COM0

Fig. 28 LCD drive waveform (1/3 bias)

36

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

Then the program executes from the reset vector address.

Usually, a program is designed so that data can be written into the

watchdog timer control register before the watchdog timer H

underflows. If data is not written once into the watchdog timer con-

trol register, the watchdog timer does not function.

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, be-

cause of a software run-away).

The watchdog timer consists of an 8-bit watchdog timer L and a 6-

bit watchdog timer H.

At execution of the STP instruction, both clock and watchdog timer

stops. At the same time that the stop mode is released, the watch-

dog timer restarts a count (Note). On the other hand, at execution

of the WIT instruction, the watchdog timer does not stop.

Initial Value of Watchdog Timer

At reset or when writing data into the watchdog timer control reg-

ister, the watchdog timer H is set to “3F16” and the watchdog timer

L is set to “FF16”. As a write instruction, it is possible to use any in-

struction that can cause a write signal such as STA, LDM and

CLB. Write data except bit 7 has no significance and the above

value is set independently.

The time from execution of writing to the watchdog timer control

register until an underflow of the watchdog timer register H is as

follows: (When bit 7 of the watchdog timer control register is “0”)

Middle / High-speed mode (f(XIN)=8 MHz).................. 32.768 ms

•

Low-speed mode (f(XCIN)=32 kHz) ..................................... 8.19 s

Note: During the stop release wait time [XIN (or XCIN) : about 8200

clock cycles], the watchdog timer counts.

Watchdog Timer Operation

The watchdog timer stops at reset and starts a countdown by writ-

ing to the watchdog timer control register. When the watchdog

timer H underflows, an internal reset occurs, and the reset status

is released after waiting the reset release time.

Accordingly, does not underflow the watchdog timer H.

When writing to

watchdog timer

control register

Data bus

XCIN

When writing to

watchdog timer control

set “FF16”

register

set “3F16”

“0”

“1”

Internal system

Watchdog timer L (8)

clock selection bit

(Note)

Watchdog timer H (6)

“1”

1/16

Watchdog timer H

count source selection bit

“0”

XIN

Undefined instruction

Reset

Reset circuit

Reset release wait time (about 8200 XIN clock cycles)

Note: This bit is bit 7 of CPU mode register. It selects the mode (middle/high-speed or low-speed)

Internal reset

RESET

Fig. 29 Watchdog timer block diagram

7

0

Watchdog timer control register

(WDTCON : address 0037¹⁶

)

Watchdog timer H bits (read only)

Not used (returns “1” when read)

Watchdog timer H count source selection bit

0 : Underflow from watchdog timer L

1 : f(X^IN)/16 or f(XCIN)/16

Fig. 30 Structure of watchdog timer control register

37

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

φ CLOCK OUTPUT FUNCTION

The internal system clock φ can be output from port P41 by setting

the φ output control register. Set bit 1 of the port P4 direction reg-

ister to when outputting φ clock.

7

0

φ output control register

(CKOUT : address 002A¹⁶

)

φ output control bit

0 : Port function

1 : φ clock output

Not used (return “0” when read)

Fig. 31 Structure of φ output control register

38

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RESET CIRCUIT

Address

Register contents

0016

To reset the microcomputer, RESET pin should be held at an “L”

level for 2 µs or more. Then the RESET pin is returned to an “H”

level (the power source voltage should be between 2.5 V and

5.5 V, and the oscillation should be stable), reset is released. In or-

der to give the XIN clock time to stabilize, internal operation does

not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are

connected together and 512 cycles of f(XIN)/16) are complete. Af-

ter the reset is completed, the program starts from the address

contained in address FFFD16 (high-order byte) and address

FFFC16 (low-order byte).

(000116) • • •

(

)

1

2

3

4

5

6

7

8

Port P0 direction register

Port P1 direction register

Port P2 direction register

(0003¹⁶) • • •

0016

(0005¹⁶) • • •

(0009¹⁶) • • •

0016

) Port P4 direction register

(000B¹⁶) • • •

(000D¹⁶) • • •

(000F¹⁶) • • •

(0016¹⁶) • • •

(0017¹⁶) • • •

(0019¹⁶) • • •

(001A¹⁶) • • •

(001B¹⁶) • • •

(001D¹⁶) • • •

(0020¹⁶) • • •

(0021¹⁶) • • •

(0022¹⁶) • • •

(0023¹⁶) • • •

(0024¹⁶) • • •

(0025¹⁶) • • •

(0026¹⁶) • • •

(0027¹⁶) • • •

(0028¹⁶) • • •

(0029¹⁶) • • •

(002A¹⁶) • • •

(0037¹⁶) • • •

Port P5 direction register

Port P6 direction register

Port P7 direction register

0016

)

0

1

0

1

0

1

0

1

0

1

0

1

0

) PULL register A

Make sure that the reset input voltage is less than 0.5 V for VCC of

2.5 V (Extended operating temperature version: the reset input

voltage is less than 0.6V for VCC of 3.0V).

( 9 )

(10)

(11)

(12)

(13)

PULL register B

0016

Serial I/O1 status register

Serial I/O1 control register

UART control register

Serial I/O2 control register

0

0016

0

0016

FF16

0116

FF16

0016

(14) Timer X (low-order)

Power on

(15)

(16)

(17)

(18)

(19)

Timer X (high-order)

Timer Y (low-order)

Timer Y (high-order)

Timer 1

(Note)

Power source

voltage

RESET

VCC

0V

Reset input

voltage

0.2V^CC

0V

Timer 2

Note. Reset release voltage : V^CC= 2.5V

(Extended operating temperature version : 3.0V)

(20) Timer 3

(21)

Timer X mode register

(22) Timer Y mode register

(23) Timer 123 mode register

RESET

VCC

Power source voltage

detection circuit

(24)

(25)

(26)

(27)

(28)

φ output control register

1

0

1

0

1

0

1

0

Watchdog timer control register

Segment output enable register (0038¹⁶) • • •

0016

LCD mode register

(0039¹⁶) • • •

Interrupt edge selection register (003A¹⁶) • • •

(29) CPU mode register

(003B¹⁶) • • •

(003C¹⁶) • • •

0

1

Interrupt request register 1

Interrupt request register 2

(30)

(31)

0016

00¹⁶

0016

Fig. 32 Example of reset circuit

(003D¹⁶) • • •

(32) Interrupt control register 1

(003E¹⁶) • • •

(33)

(34)

Interrupt control register 2 (003F16) • • •

Processor status register

(PS)

✕

1

(35) Program counter

(PC

H

)

Contents of address FFFD16

Contents of address FFFC16

(PC

L

Note.

✕ : Undefined

The contents of all other registers and RAM are undefined

at poweron reset, so they must be initialized by software.

Fig. 33 Internal state of microcomputer immediately after re-

set

39

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

X^IN

φ

RESET

Internal reset

Reset address from

vector table

Address

Data

?

AD^H,ADL

FFFC

FFFD

ADH

ADL

SYNC

•

Notes 1 : X^INand φ are in the relation : f(XIN) = 8 f(φ)

Notes 2 : A question mark (?) indicates an undefined status that depens on the previous status.

XIN : about 8200

clock cycles

Fig. 34 Reset sequence

40

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

CLOCK GENERATING CIRCUIT

Oscillation Control

The 3820 group has two built-in oscillation circuits. An oscillation

circuit can be formed by connecting a resonator between XIN and

XOUT (XCIN and XCOUT). Use the circuit constants in accordance

with the resonator manufacturer's recommended values. No exter-

nal resistor is needed between XIN and XOUT since a feed-back re-

sistor exists on-chip. However, an external feed-back resistor is

needed between XCIN and XCOUT.

Stop mode

If the STP instruction is executed, the internal clock φ stops at an

“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”

and timer 2 is set to “0116”.

Either XIN or XCIN divided by 16 is input to timer 1 as count

source, and the output of timer 1 is connected to timer 2.

The bits of the timer 123 mode register except bit 4 are cleared to

“0”. Set the timer 1 and timer 2 interrupt enable bits to disabled

(“0”) before executing the STP instruction.

To supply a clock signal externally, input it to the XIN pin and make

the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit

cannot directly input clocks that are externally generated. Accord-

ingly, be sure to cause an external resonator to oscillate.

Immediately after poweron, only the XIN oscillation circuit starts

oscillating, and XCIN and XCOUT pins function as I/O ports. The

pull-up resistor of XCIN and XCOUT pins must be made invalid to

use the sub-clock.

Oscillator restarts at reset or when an external interrupt is re-

ceived, but the internal clock φ is not supplied to the CPU until

timer 2 underflows. This allows time for the clock circuit oscillation

to stabilize.

Wait mode

If the WIT instruction is executed, the internal clock φ stops at an

“H” level. The states of XIN and XCIN are the same as the state be-

fore the executing the WIT instruction. The internal clock restarts

at reset or when an interrupt is received. Since the oscillator does

not stop, normal operation can be started immediately after the

clock is restarted.

Frequency Control

Middle-speed mode

The internal clock φ is the frequency of XIN divided by 8.

After reset, this mode is selected.

High-speed mode

The internal clock φ is half the frequency of XIN.

Low-speed mode

The internal clock φ is half the frequency of XCIN.

•

A low-power consumption operation can be realized by stopping

XCIN

XCOUT

XIN

XOUT

the main clock XIN in this mode. To stop the main clock, set bit 5

of the CPU mode register to “1”.

Rf

Rd

When the main clock XIN is restarted, set enough time for oscil-

lation to stabilize by programming.

Note: If you switch the mode between middle/high-speed and low-

speed, stabilize both XIN and XCIN oscillations. The suffi-

cient time is required for the sub-clock to stabilize, espe-

cially immediately after poweron and at returning from stop

mode. When switching the mode between middle/high-

speed and low-speed, set the frequency on condition that

f(XIN)>3f(XCIN).

C

COUT

CIN

COUT

CCIN

Fig. 35 Ceramic resonator circuit

XCIN

XCOUT

XIN

XOUT

Rf

Open

Rd

External oscillation

circuit

CCOUT

CCIN

VCC

VSS

Fig. 36 External clock input circuit

41

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

XCOUT

XCIN

"0"

"1"

Port X

C

switch bit

Timer 1 count

source selection

bit

Timer 2 count

source selection

bit

Internal system clock selection bit

(Note 1)

XIN

XOUT

"1"

Low-speed mode

"0"

Timer 1

Timer 2

1/4

1/2

Middle/High-speed mode

1/2

"0"

"1"

Main clock division ratio selection bit

Middle-speed mode

Timing φ

(Internal system clock)

High-speed mode

or Low-speed mode

Main clock stop bit

S

R

Q

S

R

S

R

Q

WIT

instruction

STP instruction

Reset

Interrupt disable flag I

Interrupt request

Note : When using the low-speed mode, set the port XC switch bit to "1" .

Fig. 37 Clock generating circuit block diagram

42

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Reset

CM6

"1"

Middle-speed mode (f(φ) =1 MHz)

High-speed mode (f(φ) =4MHz)

CM7=0(8MHz selected)

CM6=0(High-speed)

CM5=0(8MHz oscillating)

CM4=0(32kHz stopped)

"0"

CM7=0(8MHz selected)

CM6=1(Middle-speed)

CM5=0(8MHz oscillating)

CM4=0(32kHz stopped)

CM6

"1"

Middle-speed mode (f(φ) =1 MHz)

High-speed mode (f(φ) =4MHz)

"0"

CM7=0(8MHz selected)

CM6=1(Middle-speed)

CM5=0(8MHz oscillating)

CM4=1(32kHz oscillating)

CM7=0(8MHz selected)

CM6=0(High-speed)

CM5=0(8MHz oscillating)

CM4=1(32kHz oscillating)

Low-speed mode (f(φ) =16 kHz)

CM6

"1"

CM7=1(32kHz selected)

CM6=1(Middle-speed)

CM5=0(8MHz oscillating)

CM4=1(32kHz oscillating)

CM7=1(32kHz selected)

CM6=0(High-speed)

CM5=0(8MHz oscillating)

CM4=1(32kHz oscillating)

4

7

CPU mode register

(CPUM : address 003B16)

CM4 : Port Xc switch bit

0: I/O port

1: X^CIN, XCOUT

CM5 : Main clock (XIN–XOUT) stop bit

0: Oscillating

1: Stopped

CM6: Main clock division ratio selection bit

0: f(X^IN)/2 (high-speed mode)

1: f(X^IN)/8 (middle-speed mode)

CM7: Internal system clock selection bit

0: X^IN–XOUT selected

Low-speed mode (f(φ) =16 kHz)

CM6

"1"

CM7=1(32kHz selected)

CM6=0(High-speed)

CM5=1(8MHz stopped)

CM4=1(32kHz oscillating)

CM7=1(32kHz selected)

CM6=1(Middle-speed)

CM5=1(8MHz stopped)

CM4=1(32kHz oscillating)

(middle-/high-speed mode)

1: X^CIN–XCOUT selected

(low-speed mode)

Notes

1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)

2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wati

mode is released.

3: Timer and LCD operate in the wait mode.

4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and

timer 2.

5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2.

6: Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-

speed mode.

7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

Fig. 38 State transitions of internal clock φ

43

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON PROGRAMMING

Serial I/O

Processor Status Register

In clock synchronous serial I/O, if the receive side is using an ex-

ternal clock and it is to output the SRDY signal, set the transmit en-

able bit, the receive enable bit, and the SRDY output enable bit to

“1”.

The contents of the processor status register (PS) after a reset are

undefined, except for the interrupt disable flag (I) which is “1”. Af-

ter a reset, initialize flags which affect program execution.

In particular, it is essential to initialize the index X mode (T) and

the decimal mode (D) flags because of their effect on calculations.

Serial I/O1 continues to output the final bit from the TXD pin after

transmission is completed. The SOUT2 pin from serial I/O2 goes to

high impedance after transmission is completed.

Interrupts

The contents of the interrupt request bits do not change immedi-

ately after they have been written. After writing to an interrupt re-

quest register, execute at least one instruction before performing a

BBC or BBS instruction.

Instruction Execution Time

The instruction execution time is obtained by multiplying the fre-

quency of the internal clock φ by the number of cycles needed to

execute an instruction.

The number of cycles required to execute an instruction is shown

in the list of machine instructions.

Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to

“1”, then execute an ADC or SBC instruction. Only the ADC and

SBC instructions yield proper decimal results. After executing an

ADC or SBC instruction, execute at least one instruction before

executing a SEC, CLC, or CLD instruction.

The frequency of the internal clock φ is half of the XIN frequency.

In decimal mode, the values of the negative (N), overflow (V), and

zero (Z) flags are invalid.

The carry flag can be used to indicate whether a carry or borrow

has occurred. Initialize the carry flag before each calculation.

Clear the carry flag before an ADC and set the flag before an

SBC.

Timers

If a value n (between 0 and 255) is written to a timer latch, the fre-

quency division ratio is 1/(n + 1).

Multiplication and Division Instructions

The index mode (T) and the decimal mode (D) flags do not affect

the MUL and DIV instruction.

The execution of these instructions does not change the contents

of the processor status register.

Ports

The contents of the port direction registers cannot be read.

The following cannot be used:

• The data transfer instruction (LDA, etc.)

• The operation instruction when the index X mode flag (T) is “1”

• The addressing mode which uses the value of a direction regis-

ter as an index

• The bit-test instruction (BBC or BBS, etc.) to a direction register

• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a

direction register

Use instructions such as LDM and STA, etc., to set the port direc-

tion registers.

44

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM produc-

tion:

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version and built-

in EPROM version can be read or programmed with a general-

purpose PROM programmer using a special programming

adapter. Set the address of PROM programmer in the user ROM

area.

(1) Mask ROM Order Confirmation Form

(2) Mark Specification Form

(3) Data to be written to ROM, in EPROM form (three identical

copies)

Package

80P6N-A

80P6S-A

80P6D-A

80D0

Name of Programming Adapter

PCA4738F-80A

PCA4738G-80

PCA4738H-80

PCA4738L-80A

The PROM of the blank One Time PROM version is not tested or

screened in the assembly process and following processes. To en-

sure proper operation after programming, the procedure shown in

Figure 39 is recommended to verify programming.

Programming with PROM

programmer

Screening (Caution)

(150°C for 40 hours)

Verification with

PROM programmer

Functional check in

target device

The screening temperature is far higher

than the storage temperature. Never

expose to 150 °C exceeding 100 hours.

Caution :

Fig. 39 Programming and testing of One Time PROM version

45

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Conditions

Ratings

Unit

V

VCC

Power source voltage

–0.3 to 7.0

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60, P61, P70, P71

VI

–0.3 to VCC +0.3

V

All voltages are based on VSS.

Output transistors are cut off.

VI

Input voltage VL1

–0.3 to VL2

VL1 to VL3

V

Input voltage VL2

Input voltage VL3

VL2 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to VL3 +0.3

Input voltage RESET, XIN

At output port

VO

Output voltage P00–P07, P10–P17

Output voltage P30–P37

At segment output

Output voltage P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71

–0.3 to VCC +0.3

V

Output voltage SEG0–SEG15

Output voltage XOUT

Power dissipation

VO

–0.3 to VL3 +0.3

–0.3 to VCC +0.3

300

V

VO

Ta = 25 °C

Pd

mW

°C

Operating temperature

Storage temperature

Topr

Tstg

–20 to 85

–40 to 125

(VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

RECOMMENDED OPERATING CONDITIONS

Limits

Symbol

Parameter

Unit

V

Min.

4.0

2.5

Typ.

5.0

0

Max.

5.5

High-speed mode f(XIN)=8 MHz

Middle-speed mode f(XIN)=8 MHz

Low-speed mode

VCC

Power source voltage

5.5

VSS

VIH

Power source voltage

“H” input voltage

V

P00–P07, P10–P17, P30–P37, P41, P45, P47, P51,

P53, P56, P61, P70, P71 (CM4=0)

0.7 VCC

0.8 VCC

VCC

“H” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

V

VIH

“H” input voltage

“L” input voltage

RESET

XIN

0.8 VCC

VCC

V

P00–P07, P10–P17, P30–P37, P40, P41, P45, P47,

P51, P53, P56, P61, P70, P71 (CM4=0)

VIL

0

0.3 VCC

0.2 VCC

V

“L” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

VIL

“L” input voltage

RESET

XIN

0

0.2 VCC

V

46

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

–P0 , P1 –P1

Unit

Min.

Typ.

Max.

–40

40

ΣIOH(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOL(avg)

“H” total peak output current

“L” total peak output current

P0

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

–P0 , P1 –P1 , P2 –P2 (Note 1)

“H” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

“L” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

0

7

0

7

, P2

0

–P2

7

(Note 1)

mA

0

7

0

7

0

7

40

“H” total average output current P0

0

7

0

7

0

7

–20

20

0

7

0

7

0

7

20

“H” peak output current

P00–P07, P10–P17, P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71 (Note 2)

IOH(peak)

–5

5

mA

IOL(peak)

“L” peak output current

P00–P07, P10–P17 (Note 2)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 2)

10

mA

IOH(avg)

“H” average output current

P00–P07, P10–P17 (Note 3)

–1.0

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

–2.5

2.5

IOL(avg)

“L” average output current

P00–P07, P10–P17 (Note 3)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

5.0

4.0

mA

Clock input frequency

for timers X and Y

(duty cycle 50 %)

4.0 V ≤ VCC ≤ 5.5 V

VCC ≤ 4.0 V

MHz

f(CNTR0)

f(CNTR1)

(2XVCC)–4

MHz

High-speed mode (4.0 V ≤ VCC ≤ 5.5 V)

High-speed mode (VCC ≤ 4.0 V)

Middle-speed mode

8.0

Main clock input oscillation

frequency (Note 4)

(4XVCC)–8 MHz

f(XIN)

8.0

50

MHz

kHz

Sub-clock input oscillation frequency (Note 4, 5)

f(XCIN)

32.768

Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.

3: The average output current is an average value measured over 100 ms.

4: When the oscillation frequency has a duty cycle of 50 %.

5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than

f(XIN)/3.

47

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (VCC =4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Test conditions

Unit

V

Min.

Typ.

Max.

VCC–2.0

IOH = –0.1 mA

VOH

“H” output voltage P0

0

–P0

7

, P1

0

–P1

–P4

7

, P3

0

–P3

7

IOH = –25 µA

VCC = 2.5 V

IOH = –5 mA

IOH = –1.25 mA

VCC = 2.5 V

IOL = 5 mA

VCC–1.0

V

VCC–2.0

VCC–0.5

V

“H” output voltage P2

P6

0

–P2

, P6

7

1

, P4

1

7

1

,P50

–P5

7

,

VOH

, P7

0

, P7

(Note 1)

VCC–1.0

V

2.0

0.5

IOL = 1.25 mA

VCC = 2.5 V

IOL = 10 mA

IOL = 2.5 mA

VCC = 2.5 V

“L” output voltage P0

0

–P0

7

, P1

0

–P1

–P4

7

, P3

0

–P3

–P5

7

VOL

V

1.0

V

2.0

0.5

“L” output voltage P2

P6

0

–P2

, P6

7

1

, P4

1

7

1

, P5

0

,

, P7

0

, P7

(Note 1)

1.0

V

Hysteresis

CNTR

D, SCLK1, SIN2, SCLK2

RESET

0

, CNTR

1

, INT

0

–INT3, P2

0

–P2

7

VT+ – VT–

0.5

V

R

X

RESET: VCC=2.5 V to 5.5 V

VI = VCC

µA

5.0

Pull-downs “off”

VCC= 5.0 V, VI = VCC

Pull-downs “on”

“H” input current

P0

0

–P0

7

, P1

0

–P1

–P4

7

, P3

0

–P3

–P5

7

IIH

30

70

25

140

VCC= 3.0 V, VI = VCC

Pull-downs “on”

µA

6.0

45

5.0

P2

P6

0

–P2

, P6

7

1

, P4

0

7

1

, P5

0

,

IIH

VI = VCC

, P7

0

, P7

VI = VCC

IIH

“H” input current

“L” input current

RESET

µA

X

IN

4.0

P0

P4

0

–P0

, P7

7

0

, P1

0

–P1

7

, P3

0

–P3

–P5

7

,

µA

–5.0

IIL

VI = VSS

Pull-ups “off”

VCC= 5.0 V, VI = VSS

Pull-ups “on”

“L” input current

P2

P6

0

–P2

, P6

7

1

, P4

1

–P4

, P5

0

–30

–6

–70

–25

µA

IIL

–140

–45

, P7

1

VCC= 3.0 V, VI = VSS

Pull-ups “on”

IIL

VI = VSS

“L” input current

RAM hold voltage

RESET

µA

V

–5.0

IIL

VI = VSS

X

IN

–4.0

VRAM

When clock is stopped

2.0

5.5

Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the

value above mentioned.

48

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Test conditions

Unit

mA

Min.

Typ.

Max.

13

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz

6.4

1.6

25

f(XCIN) = 32.768 kHz

Output transistors “off”

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

3.2

36

mA

Output transistors “off”

• Low-speed mode, VCC = 5V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 5 V, Ta = 25°C

f(XIN) = stopped

ICC

Power source current

7.0

15

14.0

22

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

• Low-speed mode, VCC = 3 V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 3V, Ta = 25°C

f(XIN) = stopped

4.5

0.1

9.0

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

All oscillation stopped

(in STP state)

Output transistors “off”

1.0

10

Ta = 25 °C

Ta = 85 °C

49

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Unit

Min.

2

Max.

tw(RESET)

tc(XIN)

Reset input “L” pulse width

µs

ns

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

125

45

twH(XIN)

twL(XIN)

40

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

250

105

80

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

800

370

220

100

1000

400

200

t

su(R

X

D–SCLK1

D)

)

h(SCLK1–R

X

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

TIMING REQUIREMENTS 2(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Unit

Min.

Max.

tw(RESET)

tc(XIN)

Reset input “L” pulse width

2

µs

ns

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

125

45

twH(XIN)

twL(XIN)

40

500/

tc(CNTR)

CNTR0, CNTR1 input cycle time

ns

(VCC–2)

250/

(VCC–2)–20

twH(CNTR)

CNTR0, CNTR1 input “H” pulse width

250/

(VCC–2)–20

twL(CNTR)

CNTR0, CNTR1 input “L” pulse width

ns

twH(INT)

twL(INT)

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

ns

230

2000

950

400

200

2000

950

400

300

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

t

su(R

X

D–SCLK1

D)

)

h(SCLK1–R

X

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).

50

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SWITCHING CHARACTERISTICS 1(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

Min.

Max.

Typ.

twH(SCLK1)

twL(SCLK1)

Serial I/O1 clock output “H” pulse width

ns

t

c(SCLK1

)

/2–30

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

t

d(SCLK1–T

v(SCLK1–T

X

D)

140

XD)

–30

tr(SCLK1)

tf(SCLK1)

30

twH(SCLK2)

twL(SCLK2)

t

c(SCLK2

)/2–160

t

c(SCLK2

)

/2–160

t

d(SCLK2–SOUT2

)

0.2✕tC(SCLK2)

v(SCLK2–SOUT2

)

Serial I/O2 output valid time

0

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

40

30

10

Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

SWITCHING CHARACTERISTICS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

Min.

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

Serial I/O1 clock output “H” pulse width

t

c(SCLK1

)

/2–50

ns

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

c(SCLK1

t

d(SCLK1–T

v(SCLK1–T

X

D)

350

XD)

–30

tr(SCLK1)

tf(SCLK1)

50

twH(SCLK2)

twL(SCLK2)

tc(SCLK2

)

/2–240

tc(SCLK2

/2–240

t

d(SCLK2–SOUT2

)

0.2✕t^C(SCLK2)

v(SCLK2–SOUT2

)

Serial I/O2 output valid time

0

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

50

20

Notes1:When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

51

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS (Extended Operating Temperature Version)

Symbol

Parameter

Conditions

Ratings

Unit

V

VCC

Power source voltage

–0.3 to 7.0

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60, P61, P70, P71

VI

–0.3 to VCC +0.3

V

All voltages are based on VSS.

Output transistors are cut off.

VI

Input voltage VL1

–0.3 to VL2

VL1 to VL3

V

Input voltage VL2

Input voltage VL3

VL2 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to VL3 +0.3

Input voltage RESET, XIN

At output port

VO

Output voltage P00–P07, P10–P17

Output voltage P30–P37

At segment output

Output voltage P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71

–0.3 to VCC +0.3

V

Output voltage SEG0–SEG15

Output voltage XOUT

Power dissipation

VO

–0.3 to VL3 +0.3

–0.3 to VCC +0.3

300

V

VO

Ta = 25 °C

Pd

mW

°C

Operating temperature

Storage temperature

Topr

Tstg

–40 to 85

–65 to 150

RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version)

(VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C and VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

V

Min.

4.0

Typ.

5.0

Max.

5.5

High-speed mode f(XIN)=8 MHz

Middle-speed mode

f(XIN)=8 MHz

Ta = –20 to 85 °C

Ta = –40 to –20 °C

Ta = –20 to 85 °C

Ta = –40 to –20 °C

2.5

5.0

5.5

Power source voltage

VCC

3.0

2.5

3.0

5.0

5.5

Low-speed mode

Power source voltage

“H” input voltage

VSS

VIH

0

V

P00–P07, P10–P17, P30–P37, P41, P45, P47, P51,

P53, P56, P61, P70, P71 (CM4=0)

VCC

0.7 VCC

0.8 VCC

“H” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

V

VIH

VCC

0.8 VCC

V

“H” input voltage

“L” input voltage

RESET

XIN

P00–P07, P10–P17, P30–P37, P40, P41, P45, P47,

P51, P53, P56, P61, P70, P71 (CM4=0)

0

VIL

0.3 VCC

0.2 VCC

V

“L” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

“L” input voltage

RESET

XIN

VIL

0

0.2 VCC

V

52

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version)

(VCC = 3.0 to 5.5 V, Ta = –40 to –20 °C and VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C unless otherwise noted.)

Limits

Symbol

Parameter

–P0 , P1 –P1

Unit

Min.

Typ.

Max.

–40

40

ΣIOH(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOL(avg)

“H” total peak output current

“L” total peak output current

P0

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

–P0 , P1 –P1 , P2 –P2 (Note 1)

“H” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

“L” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

0

7

0

7

, P2

0

–P2

7

(Note 1)

mA

0

7

0

7

0

7

40

“H” total average output current P0

0

7

0

7

0

7

–20

20

0

7

0

7

0

7

20

“H” peak output current

P00–P07, P10–P17, P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71 (Note 2)

IOH(peak)

–5

5

mA

IOL(peak)

“L” peak output current

P00–P07, P10–P17 (Note 2)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 2)

10

mA

IOH(avg)

“H” average output current

P00–P07, P10–P17 (Note 3)

–1.0

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

–2.5

2.5

IOL(avg)

“L” average output current

P00–P07, P10–P17 (Note 3)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

5.0

4.0

mA

Clock input frequency

for timers X and Y

(duty cycle 50 %)

4.0 V ≤ VCC ≤ 5.5 V

VCC ≤ 4.0 V

MHz

f(CNTR0)

f(CNTR1)

(2XVCC)–4

MHz

High-speed mode (4.0 V ≤ VCC ≤ 5.5 V)

High-speed mode (VCC ≤ 4.0 V)

Middle-speed mode

8.0

Main clock input oscillation

frequency (Note 4)

(4XVCC)–8 MHz

f(XIN)

8.0

50

MHz

kHz

Sub-clock input oscillation frequency (Note 4, 5)

f(XCIN)

32.768

Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.

3: The average output current is an average value measured over 100 ms.

4: When the oscillation frequency has a duty cycle of 50 %.

5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than

f(XIN)/3.

53

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)

(VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, and VCC =3.0 to 5.5 V, Ta = –40 to –20 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Test conditions

IOH = –2.5 mA

Unit

V

Min.

Max.

VCC–2.0

VOH

“H” output voltage P0

0

–P0

7

, P1

0

1

–P17, P30–P37

IOH = –0.6 mA

VCC = 3.0 V

IOH = –5 mA

IOH = –1.25 mA

VCC = 3.0 V

IOL = 5 mA

VCC–0.9

V

VCC–2.0

VCC–0.5

V

“H” output voltage P2

P6

0

–P2

, P6

7, P4

–P4

, P7

7

1

,P5

(Note)

0

–P5

7

,

VOH

1

, P7

0

VCC–0.9

V

2.0

0.5

IOL = 1.25 mA

VCC = 3.0 V

IOL = 10 mA

IOL = 2.5 mA

VCC = 3.0 V

“L” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P3

0

–P3

–P5

7

VOL

V

1.1

V

2.0

0.5

“L” output voltage P2

P6

0

–P2

, P6

7, P4

1

–P4

, P7

7

1

, P5

(Note)

0

,

1

, P7

0

1.1

V

Hysteresis

CNTR

0

, CNTR

1

, INT

0

–INT

3

, P2

0

–P2

7

VT+ – VT–

0.5

V

RXD, SCLK1, SIN2, SCLK2

RESET

RESET: VCC=3.0 V to 5.5 V

VI = VCC

µA

5.0

Pull-downs “off”

VCC= 5.0 V, VI = VCC

Pull-downs “on”

“H” input current

P0

0

–P0

7, P1

0

–P1

7, P3

0

–P3

7

IIH

30

70

25

170

VCC= 3.0 V, VI = VCC

Pull-downs “on”

µA

6.0

55

5.0

P2

P6

0

–P2

, P6

7, P4

0

–P4

, P7

7

1

, P5

0

–P5

,

IIH

VI = VCC

1

, P7

0

VI = VCC

IIH

“H” input current

“L” input current

RESET

µA

X

IN

4.0

P0

P4

0

–P0

, P7

7, P1

–P1

–P4

7

, P3

0

–P3

–P5

7

,

µA

–5.0

IIL

0

VI = VSS

Pull-ups “off”

VCC= 5.0 V, VI = VSS

Pull-ups “on”

“L” input current

P2

P6

0

–P2

, P6

7, P4

1

, P50

–30

–6

–70

–25

µA

IIL

–140

1

, P7

1

VCC= 3.0 V, VI = VSS

Pull-ups “on”

–45

IIL

VI = VSS

“L” input current

RAM hold voltage

RESET

µA

V

–5.0

IIL

VI = VSS

X

IN

–4.0

VRAM

When clock is stopped

2.0

5.5

Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the

value above mentioned.

54

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version)

(VCC =3.0 to 5.5 V, Ta = –40 to –20 °C and VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Test conditions

Unit

mA

Min.

Max.

13

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz

6.4

1.6

25

f(XCIN) = 32.768 kHz

Output transistors “off”

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

3.2

36

mA

Output transistors “off”

• Low-speed mode, VCC = 5V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 5 V, Ta = 25°C

f(XIN) = stopped

ICC

Power source current

7.0

15

14.0

22

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

• Low-speed mode, VCC = 3 V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 3V, Ta = 25°C

f(XIN) = stopped

4.5

0.1

9.0

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

All oscillation stopped

(in STP state)

Output transistors “off”

Ta = 25 °C

Ta = 85 °C

1.0

10

55

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1 (Extended Operating Temperature Version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Unit

Min.

2

Max.

tw(RESET)

tc(XIN)

Reset input “L” pulse width

µs

ns

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

125

45

twH(XIN)

twL(XIN)

40

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

250

105

80

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

800

370

220

100

1000

400

200

t

su(R

XD–SCLK1

)

h(SCLK1–RXD)

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

TIMING REQUIREMENTS 2 (Extended Operating Temperature Version)

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –40 to –20 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

Min.

Typ.

Max.

tw(RESET)

tc(XIN)

Reset input “L” pulse width

2

µs

ns

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

125

45

twH(XIN)

twL(XIN)

40

500/

(VCC–2)

tc(CNTR)

CNTR0, CNTR1 input cycle time

ns

250/

(VCC–2)–20

twH(CNTR)

CNTR0, CNTR1 input “H” pulse width

250/

(VCC–2)–20

twL(CNTR)

CNTR0, CNTR1 input “L” pulse width

ns

twH(INT)

twL(INT)

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

230

2000

950

400

200

2000

950

400

300

ns

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

t

su(R

X

D–SCLK1

)

h(SCLK1–R

X

D)

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).

56

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Serial I/O1 clock output “H” pulse width

Unit

Min.

Max.

140

twH(SCLK1)

twL(SCLK1)

t

c(SCLK1

)

/2–30

ns

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

c(SCLK1

t

d(SCLK1–T

v(SCLK1–T

X

D)

X

D)

–30

tr(SCLK1)

tf(SCLK1)

30

twH(SCLK2)

twL(SCLK2)

t

c(SCLK2

)

/2–160

t

)/2–160

t

d(SCLK2–SOUT2

v(SCLK2–SOUT2

)

0.2✕tC(SCLK2)

)

Serial I/O2 output valid time

0

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

40

30

10

Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version)

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, and VCC = 3.0 to 4.0 V, Ta = –40 to –20 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

Min.

Typ.

Max.

350

twH(SCLK1)

twL(SCLK1)

Serial I/O1 clock output “H” pulse width

t

c(SCLK1

)

/2–50

ns

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

c(SCLK1

t

d(SCLK1–T

v(SCLK1–T

X

D)

X

D)

–30

tr(SCLK1)

tf(SCLK1)

50

twH(SCLK2)

twL(SCLK2)

t

c(SCLK2

)

/2–240

t

/2–240

t

d(SCLK2–SOUT2

v(SCLK2–SOUT2

)

0.2✕t^C(SCLK2)

)

Serial I/O2 output valid time

0

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

50

20

Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

Measurement output pin

1kΩ

100pF

Measurement output pin

100pF

CMOS output

N-channel open-drain output (Note)

Note:When bit 4 of the UART

control register (address 001B16) is “1”.

(N-channel open-drain output mode)

Fig.40 Circuit for measuring output switching characteristics

57

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ABSOLUTE MAXIMUM RATINGS (Low Power Source Voltage Version)

Symbol

Parameter

Conditions

Ratings

Unit

V

VCC

Power source voltage

–0.3 to 7.0

Input voltage P00–P07, P10–P17, P20–P27,

P30–P37, P40–P47, P50–P57,

P60, P61, P70, P71

VI

–0.3 to VCC +0.3

V

All voltages are based on VSS.

Output transistors are cut off.

VI

Input voltage VL1

–0.3 to VL2

VL1 to VL3

V

Input voltage VL2

Input voltage VL3

VL2 to VCC +0.3

–0.3 to VCC +0.3

–0.3 to VL3 +0.3

Input voltage RESET, XIN

At output port

VO

Output voltage P00–P07, P10–P17

Output voltage P30–P37

At segment output

Output voltage P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71

–0.3 to VCC +0.3

V

Output voltage SEG0–SEG15

Output voltage XOUT

Power dissipation

VO

–0.3 to VL3 +0.3

–0.3 to VCC +0.3

300

V

VO

Ta = 25 °C

Pd

mW

°C

Operating temperature

Storage temperature

Topr

Tstg

–20 to 85

–40 to 150

RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version)

(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Unit

V

Min.

4.0

2.2

Typ.

5.0

0

Max.

5.5

High-speed mode f(XIN)=8 MHz

Middle-speed mode f(XIN)=8 MHz

Low-speed mode

VCC

Power source voltage

5.5

VSS

VIH

Power source voltage

“H” input voltage

V

P00–P07, P10–P17, P30–P37, P41, P45, P47, P51,

P53, P56, P61, P70, P71 (CM4=0)

0.7 VCC

0.8 VCC

VCC

“H” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

V

VIH

“H” input voltage

“L” input voltage

RESET

XIN

0.8 VCC

VCC

V

P00–P07, P10–P17, P30–P37, P40, P41, P45, P47,

P51, P53, P56, P61, P70, P71 (CM4=0)

VIL

0

0.3 VCC

0.2 VCC

V

“L” input voltage

P20–P27, P42–P44, P46, P50, P52, P54, P55, P57,

P60

VIL

“L” input voltage

RESET

XIN

0

0.2 VCC

V

0.2 VCC

58

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version)

(VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

–P0 , P1 –P1

Unit

Min.

Max.

–40

40

ΣIOH(peak)

ΣIOL(peak)

ΣIOH(avg)

ΣIOL(avg)

“H” total peak output current

“L” total peak output current

P0

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

–P0 , P1 –P1 , P2 –P2 (Note 1)

“H” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 (Note 1)

“L” total average output current P41–P47,P50–P57, P60, P61, P70, P71 (Note 1)

0

7

0

7

, P2

0

–P2

7

(Note 1)

mA

0

7

0

7

0

7

40

“H” total average output current P0

0

7

0

7

0

7

–20

20

0

7

0

7

0

7

20

“H” peak output current

P00–P07, P10–P17, P20–P27, P41–P47, P50–P57,

P60, P61, P70, P71 (Note 2)

IOH(peak)

–5

5

mA

IOL(peak)

“L” peak output current

P00–P07, P10–P17 (Note 2)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 2)

10

mA

IOH(avg)

“H” average output current

P00–P07, P10–P17 (Note 3)

–1.0

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

–2.5

2.5

IOL(avg)

“L” average output current

P00–P07, P10–P17 (Note 3)

P20–P27, P41–P47, P50–P57, P60, P61, P70, P71

(Note 3)

5.0

mA

Clock input frequency

for timers X and Y

(duty cycle 50 %)

4.0 V ≤ VCC ≤ 5.5 V

4.0

MHz

f(CNTR0)

f(CNTR1)

(10XVCC–4)

VCC ≤ 4.0 V

MHz

9

8.0

High-speed mode (4.0 V ≤ VCC ≤ 5.5 V)

(20XVCC–8)

Main clock input oscillation

frequency (Note 4)

High-speed mode (VCC ≤ 4.0 V)

MHz

f(XIN)

9

Middle-speed mode

8.0

50

MHz

kHz

32.768

f(XCIN)

Sub-clock input oscillation frequency (Note 4, 5)

Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av

erage value measured over 100 ms. The total peak current is the peak value of all the currents.

2: The peak output current is the peak current flowing in each port.

3: The average output current is an average value measured over 100 ms.

4: When the oscillation frequency has a duty cycle of 50 %.

5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than

f(XIN)/3.

59

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version)

(VCC =4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol Parameter

Test conditions

IOH = –0.1 mA

Unit

V

Min.

Max.

VCC–2.0

VOH

“H” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P3

0

–P3

7

IOH = –25 µA

VCC = 2.2 V

IOH = –5 mA

IOH = –1.25 mA

VCC = 2.2 V

IOL = 5 mA

VCC–1.0

V

VCC–2.0

VCC–0.5

V

“H” output voltage P2

P6

0–P2

7

1

, P4

, P7

1–P4

,P50

–P5

7

,

VOH

0, P6

0

, P7

1

(Note)

VCC–1.0

V

2.0

0.5

IOL = 1.25 mA

VCC = 2.2 V

IOL = 10 mA

IOL = 2.5 mA

VCC = 2.2 V

“L” output voltage P0

0

–P0

7

, P1

0

–P1

7

, P3

, P5

0

–P3

7

VOL

V

1.1

V

2.0

0.5

“L” output voltage P2

P6

0–P2

7

1

, P4

, P7

1–P4

0

–P5

7

,

0, P6

0

, P71 (Note)

1.0

V

Hysteresis

CNTR

0

, CNTR

1

, INT

0

–INT

3

, P2

0

–P27

VT+ – VT–

0.5

V

R

XD, SCLK1, SIN2, SCLK2

RESET: VCC=2.2 V to 5.5 V

VI = VCC

RESET

µA

5.0

Pull-downs “off”

VCC= 5.0 V, VI = VCC

Pull-downs “on”

“H” input current

P0

0

–P0

7

, P1

0

–P1

7

, P3

, P5

0–P37

IIH

30

70

25

170

VCC= 3.0 V, VI = VCC

Pull-downs “on”

µA

6.0

55

5.0

P2

P6

0–P2

7

1

, P4

, P7

0–P4

0

–P57,

IIH

VI = VCC

0, P6

0

, P7

1

VI = VCC

IIH

“H” input current

“L” input current

RESET

8.0

4.0

µA

XIN

P0

P4

0–P0

7

0

, P1

0–P1

7

, P3

, P5

0

–P3

7

,

µA

–5.0

IIL

0, P7

VI = VSS

Pull-ups “off”

VCC= 5.0 V, VI = VSS

Pull-ups “on”

VCC= 3.0 V, VI = VSS

Pull-ups “on”

VI = VSS

“L” input current

P2

P6

0–P2

7

1

, P4

, P7

1–P4

7

–P57

IIL

–30

–6

–70

–25

µA

–140

0, P6

1

–45

IIL

“L” input current

RESET

µA

–5.0

VI = VSS

XIN

–8.0

Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the

value above mentioned.

60

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version)

(VCC =2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol Parameter

Test conditions

Unit

V

Min.

2.0

Max.

5.5

VRAM

RAM hold voltage

When clock is stopped

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz

6.4

1.6

25

13

3.2

36

mA

f(XCIN) = 32.768 kHz

Output transistors “off”

• High-speed mode, VCC = 5 V

f(XIN) = 8 MHz (in WIT state)

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 5V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 5 V, Ta = 25°C

f(XIN) = stopped

ICC

Power source current

7.0

15

14.0

22

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

• Low-speed mode, VCC = 3 V, Ta ≤ 55°C

f(XIN) = stopped

µA

f(XCIN) = 32.768 kHz

Output transistors “off”

• Low-speed mode, VCC = 3V, Ta = 25°C

f(XIN) = stopped

4.5

0.2

9.0

f(XCIN) = 32.768 kHz (in WIT state)

Output transistors “off”

All oscillation stopped

(in STP state)

Output transistors “off”

Ta = 25 °C

Ta = 85 °C

2.0

20

61

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING REQUIREMENTS 1 (Low Power Source Voltage Version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Unit

Min.

2

Max.

_____

tw(RESET)

Reset input “L” pulse width

µs

ns

tc(XIN)

Main clock input cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

125

45

twH(XIN)

twL(XIN)

40

tc(CNTR)

twH(CNTR)

twL(CNTR)

twH(INT)

twL(INT)

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

CNTR0, CNTR1 input cycle time

CNTR0, CNTR1 input “H” pulse width

CNTR0, CNTR1 input “L” pulse width

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

250

105

80

800

370

220

100

1000

400

200

t

su(R

X

D–SCLK1

D)

)

h(SCLK1–R

X

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).

TIMING REQUIREMENTS 2 (Low Power Source Voltage Version)

(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Unit

Min.

2

Max.

_____

tw(RESET)

Reset input “L” pulse width

µs

ns

125

45

tc(XIN)

Main clock iuput cycle time (XIN input)

Main clock input “H” pulse width

Main clock input “L” pulse width

twH(XIN)

twL(XIN)

40

900/

(VCC–0.4)

tc(CNTR)

CNTR0, CNTR1 input cycle time

ns

450/

(VCC–0.4)–20

450/

twH(CNTR)

CNTR0, CNTR1 input “H” pulse width

twL(CNTR)

CNTR0, CNTR1 input “L” pulse width

ns

(VCC–0.4)–20

230

2000

950

400

200

2000

950

400

300

twH(INT)

twL(INT)

INT0 to INT3 input “H” pulse width

INT0 to INT3 input “L” pulse width

Serial I/O1 clock input cycle time (Note)

Serial I/O1 clock input “H” pulse width (Note)

Serial I/O1 clock input “L” pulse width (Note)

Serial I/O1 input set up time

ns

tc(SCLK1)

twH(SCLK1)

twL(SCLK1)

t

su(R

X

D–SCLK1

)

h(SCLK1–R

X

D)

Serial I/O1 input hold time

tc(SCLK2)

Serial I/O2 clock input cycle time

Serial I/O2 clock input “H” pulse width

Serial I/O2 clock input “L” pulse width

Serial I/O2 input set up time

twH(SCLK2)

twL(SCLK2)

t

su(SIN2–SCLK2

h(SCLK2–SIN2

)

Serial I/O2 input hold time

Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous).

Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).

62

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Typ.

Symbol

Parameter

Serial I/O1 clock output “H” pulse width

Unit

Min.

Max.

140

twH(SCLK1)

twL(SCLK1)

t

c(SCLK1

)

/2–30

ns

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

c(SCLK1

t

d(SCLK1–T

v(SCLK1–T

X

D)

XD)

–30

tr(SCLK1)

tf(SCLK1)

30

twH(SCLK2)

twL(SCLK2)

t

c(SCLK2

)

/2–160

t

/2–160

t

d(SCLK2–SOUT2

)

0.2✕tC(SCLK2) ns

v(SCLK2–SOUT2

)

Serial I/O2 output valid time

0

ns

tf(SCLK2)

tr(CMOS)

tf(CMOS)

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

40

30

ns

10

Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version)

(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.)

Limits

Symbol

Parameter

Serial I/O1 clock output “H” pulse width

Unit

Min.

Typ.

Max.

twH(SCLK1)

twL(SCLK1)

t

c(SCLK1

)/2–50

ns

c(SCLK1

)/2–50

Serial I/O1 clock output “L” pulse width

Serial I/O1 output delay time (Note 1)

Serial I/O1 output valid time (Note 1)

Serial I/O1 clock output rising time

Serial I/O1 clock output falling time

Serial I/O2 clock output “H” pulse width

Serial I/O2 clock output “L” pulse width

Serial I/O2 output delay time

t

d(SCLK1–T

v(SCLK1–T

X

D)

350

XD)

–30

tr(SCLK1)

tf(SCLK1)

50

twH(SCLK2)

twL(SCLK2)

t

c(SCLK2

)/2–240

t

c(SCLK2

)/2–240

t

d(SCLK2–SOUT2

)

0.2✕t^C(SCLK2)

v(SCLK2–SOUT2

)

0

Serial I/O2 output valid time

tf(SCLK2)

tr(CMOS)

tf(CMOS)

50

Serial I/O2 clock output falling time

CMOS output rising time (Note 2)

CMOS output falling time (Note 2)

20

Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

2: XOUT and XCOUT pins are excluded.

Measurement output pin

1kΩ

100pF

Measurement output pin

100pF

CMOS output

N-channel open-drain output (Note)

Note:When bit 4 of the UART

control register (address 001B16) is “1”.

(N-channel open-drain output mode)

Fig.41 Circuit for measuring output switching characteristics

63

MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

TIMING DIAGRAM

tC(CNTR)

tWL(CNTR)

tWH(CNTR)

CNTR

0

,CNTR

1

0.8VCC

0.2VCC

tWL(INT)

tWH(INT)

INT0–INT3

0.8VCC

0.2VCC

tW(RESET)

0.8VCC

RESET

0.2VCC

tC(XIN)

tWL(XIN)

tWH(XIN)

0.8VCC

XIN

0.2VCC

tC(SCLK1),tC(SCLK2)

tr

tf

t

WL(SCLK1

)

,tWL(SCLK2

)

tWH(SCLK1),tWH(SCLK2)

S

CLK1

CLK2

0.8VCC

0.2VCC

S

t

h(SCLK1-RXD)

t

su(R

X

D-SCLK1

)

h(SCLK2-SIN2

)

su(SIN2-SCLK2

)

R D

S

X

0.8VCC

0.2VCC

IN2

t

v(SCLK1-T

XD),

v(SCLK2-SOUT2

)

t

d(SCLK1-TXD),td(SCLK2-SOUT2)

T

X

D

SOUT2

64

MITSUBISHI MICROCOMPUTERS

3820Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Keep safety first in your circuit designs!

•

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of

substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

•

These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any

intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples

contained in these materials.

All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi

Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor

product distributor for the latest product information before purchasing a product listed herein.

•

Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact

Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for

transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

•

The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the

approved destination.

Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

•

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

H-DF047-C KI-9609

New publication, effective Sep. 1996.

Specifications subject to change without notice.

REVISION DESCRIPTION LIST

3820GROUP DATA SHEET

Rev.

date

Revision Description

No.

1.0 First Edition

971128

(1/1)

型号：	3820
PDF下载：	下载PDF文件查看货源
内容描述：	单片8位CMOS微机 [SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER]
分类和应用：	计算机
文件页数/大小：	66 页 / 1084 K
品牌：	MITSUBISHI [ Mitsubishi Group ]

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