System Reset (with built-in watchdog timer) MM1096
MITSUMI
Description of Operation
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1. RESET goes low when VCC rises to approximately 0.8V.
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Approximately 1µA (VCC=0.8V) of pull up current is output from RESET
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2. Capacitor CT charging starts when VCC rises to VSH (MM1096A = 3.25V, MM1096B = 4.3V). Output is in
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reset state at this time.
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3. Output reset is released (RESET goes high) after a certain time (TPR), from when CT starts charging until
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discharge (the time from when CT voltage reaches a certain threshold value 1 (= 1.4V) until CT voltage
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drops to a certain threshold value 2 (= 0.2V).
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Reset hold time : TPR is as follows.
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TPR (ms) = 500 CT (µF)
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CT charging starts again after reset release, and watchdog timer operation begins.
Clock input to the CK pin during CT charging will cause mis-operation.
4. If a clock is input (negative edge trigger) to the CK pin during CT charging, C switches from charging to
discharge.
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5. Discharge switches to charging when CT voltage drops to a certain threshold value (= 0.2V). Steps 4 and
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5 are repeated while a normal clock is input from the logic system.
6. Output goes to reset state (-R----------E---------S----------E---------T-------- goes low) when the clock ceases and CT voltage reaches reset ON
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threshold value (= 1.4V).
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The formula for CT charging time (TWD : watchdog timer monitoring time) until reset is output is as follows.
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TWD (ms) = 2500 CT (µF)
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7. Watchdog timer reset time TWR is the discharge time until CT voltage drops to reset OFF threshold value
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(= 0.2V). The formula is as follows.
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TWR (ms) = 100 CT (µF)
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After reset OFF threshold value is reached, output reset is released and CT starts charging. Thereafter,
steps 4 and 5 are repeated if a normal clock is input, and when the clock ceases, 6 and 7 are repeated.
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8. Reset is output when VCC drops to VSL (MM1096A = 3.2V, MM1096B = 4.2V). CT is charged
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simultaneously.
9. CT charging starts when VCC rises to VSH.
When VCC drops momentarily, CT charging begins after the charge is first discharged, if the time from VCC
dropping below VSL until it rises to VSH is longer than the Vcc input pulse width standard value TPI.
10.Output reset is released after VCC goes above VSH and after TPR, and the watchdog timer starts. Thereafter,
8~10 are repeated when VCC goes below VSL.
11.When power is OFF, reset is output if VCC goes below VSL.
12.When VCC drops to 0V, reset output is held until VCC reaches 0.8V.
MITSUMI [ MITSUMI ELECTRONICS, CORP. ]
