欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC10129L 参数 Datasheet PDF下载

MC10129L图片预览
型号: MC10129L
PDF下载: 下载PDF文件 查看货源
内容描述: 四路总线接收器 [Quad Bus Receiver]
分类和应用:
文件页数/大小: 7 页 / 114 K
品牌: MOTOROLA [ MOTOROLA, INC ]
 浏览型号MC10129L的Datasheet PDF文件第2页浏览型号MC10129L的Datasheet PDF文件第3页浏览型号MC10129L的Datasheet PDF文件第4页浏览型号MC10129L的Datasheet PDF文件第5页浏览型号MC10129L的Datasheet PDF文件第6页浏览型号MC10129L的Datasheet PDF文件第7页  
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Receiver
The MC10129 data inputs are compatible with, and accept TTL logic levels
as well as levels compatible with IBM–type buses. The clock, strobe, and reset
inputs accept MECL 10,000 logic levels.
The data inputs accept the bus levels, and storage elements are provided to
yield temporary latch storage of the information after receiving it from the bus.
The outputs can be strobed to allow accurate synchronization of signals and/or
connection to MECL 10,000 level buses. When the clock is low, and the reset
input is disabled, the outputs will follow the D inputs. The latches will store the
data on the rising edge of the clock. The outputs are enabled when the strobe
input is high. Unused D inputs must be tied to VCC or Gnd. The clock, strobe,
and reset inputs each have 50 k ohm pulldown resistors to VEE. They may be
left floating, if not used.
The MC10129 will operate in either of two modes. The first mode is obtained
by tying the hysteresis control input to VEE. In this mode, the input threshold
points of the D inputs are fixed. The second mode is obtained by tying the
hysteresis control input to ground. In this mode, input hysteresis is achieved as
shown in the test table. This hysteresis is desirable where extra noise margin is
required on the D inputs. The outer input pins are unaffected by the mode of
operation used.
The MC10129 is especially useful in interface applications for central
processors, mini–computers, and peripheral equipment.
PD = 750 mW typ/pkg (No Load)
tpd = 10 ns typ
VCC Max = 7.0 Vdc
MC10129
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
PIN ASSIGNMENT
GND
Q3
Q2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
Q1
Q0
D1
STROBE
CLOCK
RESET
VCC
LOGIC DIAGRAM
D0 7
D
C
R
D3
HYSTERESIS
CONTROL
14 Q0
D2
D0
VEE
D1 13
D
C
R
15 Q1
D2 6
D
C
R
3 Q2
TRUTH TABLE
D
C
X
H
L
H
L
STROBE
L
X
H
H
H
RESET
X
H
X
L
X
Qn + 1
L
L
L
Qn
H
2 Q3
X
X
L
X
H
D3 4
HYSTERESIS
CONTROL
CLOCK
RESET
STROBE
D
C
R
VCC = PIN 9
GND = PIN 1 AND 16
VEE = PIN 8
5
11
10
12
9/96
©
Motorola, Inc. 1996
3–1
REV 6