Freescale Semiconductor, Inc.
Resets and Interrupts
Table 9-1. Interrupt Vector Map
CCR
HPRIO Value to
Elevate
Vector Address
Interrupt Source
Local Enable
Mask
None
None
None
None
None
X bit
I bit
$FFFE, $FFFF Reset
None
COPCTL (CME, FCME)
COP rate selected
None
–
–
–
$FFFC, $FFFD Clock monitor fail reset
$FFFA, $FFFB COP failure reset
$FFF8, $FFF9 Unimplemented instruction trap
$FFF6, $FFF7 SWI
–
–
–
None
None
$FFF4, $FFF5 XIRQ
$FFF2, $FFF3 IRQ
INTCR (IRQEN)
RTICTL (RTIE)
TMSK1 (C0I)
TMSK1 (C1I)
TMSK1 (C2I)
TMSK1 (C3I)
TMSK1 (C4I)
TMSK1 (C5I)
TMSK1 (C6I)
TMSK1 (C7I)
TMSK2 (TOI)
PACTL (PAOVI)
PACTL (PAI)
SP0CR1 (SPIE)
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$FFF0, $FFF1 Real time interrupt
$FFEE, $FFEF Timer channel 0
$FFEC, $FFED Timer channel 1
$FFEA, $FFEB Timer channel 2
$FFE8, $FFE9 Timer channel 3
$FFE6, $FFE7 Timer channel 4
$FFE4, $FFE5 Timer channel 5
$FFE2, $FFE3 Timer channel 6
$FFE0, $FFE1 Timer channel 7
$FFDE, $FFDF Timer overflow
$FFDC, $FFDD Pulse accumulator overflow
$FFDA, $FFDB Pulse accumulator input edge
$FFD8, $FFD9 SPI serial transfer complete
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
SC1CR2
(TIE, TCIE, RIE, ILIE)
$FFD6, $FFD7 SCI 0
$FFD4, $FFD5 SCI 1
I bit
I bit
$D6
$D4
$FFD2, $FFD3 ATD0 or ATD1
$FFD0, $FFD1 MSCAN wake-up
I bit
I bit
ATDxCTL2 (ASCIE)
CRIER (WUPIE)
$D2
$D0
KWIEG[6:0] and
KWIEH[7:0]
$FFCE, $FFCF Key wake-up G or H
I bit
$CE
$FFCC, $FFCD Modulus down counter underflow
$FFCA, $FFCB Pulse Accumulator B Overflow
I bit
I bit
MCCTL (MCZI)
PBCTL (PBOVI)
$CC
$CA
CRIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
$FFC8, $FFC9 MSCAN errors
I bit
$C8
$FFC6, $FFC7 MSCAN receive
$FFC4, $FFC5 MSCAN transmit
$FFC2, $FFC3 CGM lock and limp home
$FF80–$FFC1 Reserved
I bit
I bit
I bit
I bit
CRIER (RXFIE)
CTCR (TXEIE[2:0])
PLLCR (LOCKIE, LHIE)
$C6
$C4
$C2
$80–$C0
Advance Information
68HC(9)12D60 — Rev 4.0
MOTOROLA
126
Resets and Interrupts
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