Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
9.6.2 External Reset
The CPU distinguishes between internal and external reset conditions
by sensing whether the reset pin rises to a logic one in less than eight E-
clock cycles after an internal device releases reset. When a reset
condition is sensed, the RESET pin is driven low by an internal device
for about 16 E-clock cycles, then released. Eight E-clock cycles later it is
sampled. If the pin is still held low, the CPU assumes that an external
reset has occurred. If the pin is high, it indicates that the reset was
initiated internally by either the COP system or the clock monitor.
To prevent a COP or clock monitor reset from being detected during an
external reset, hold the reset pin low for at least 32 cycles. An external
RC power-up delay circuit on the reset pin is not recommended as circuit
charge time can cause the MCU to misinterpret the type of reset that has
occurred.
9.6.3 COP Reset
The MCU includes a computer operating properly (COP) system to help
protect against software failures. When COP is enabled, software must
write $55 and $AA (in this order) to the COPRST register in order to keep
a watchdog timer from timing out. Other instructions may be executed
between these writes. A write of any value other than $55 or $AA or
software failing to execute the sequence properly causes a COP reset to
occur. In addition, windowed COP operation can be selected. In this
mode, a write to the COPRST register must occur in the last 25% of the
selected period. A premature write will also reset the part.
9.6.4 Clock Monitor Reset
If clock frequency falls below a predetermined limit when the clock
monitor is enabled, a reset occurs.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
129
Resets and Interrupts
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