®
MU9C1965A LANCAM MP
Operational Characteristics
CAM Status
/RESET Condition
Validity bits at all memory locations
Match and Full Flag outputs
Skip = 0, Empty = 1 (empty)
Enabled
CAM/RAM Partitioning
Comparison Masking
128 bits CAM, 0 bits RAM
Disabled
Address register auto-increment or auto-decrement
Source and Destination Segment counters count ranges
Address register and Next Free Address register
Page Address and Device Select registers
Control register after reset (including CT15)
Persistent Destination for Command writes
Persistent Source for Command reads
Persistent Source and Destination for Data reads and writes
Operating Mode
Disabled
00B to 11B; loaded with 00B
Contain all 0s
Contain all 0s (no change on software reset)
Contains 0008H
Instruction decoder
Status register
Comparand register
Standard
Configuration Register set
Foreground
Table 5: Device Control State After Reset
If the Address Field flag is set in a memory access
instruction, the absolute address supplied on the DQ15-0
lines will automatically load the Address register and the
instruction will execute at this new address. If the Address
Field flag is not set, the memory access occurs at the
address currently contained in the Address register. After
the execution of the instruction, the Address register
auto-increments or auto-decrements depending on the
setting of Control Register bits CT3 and CT2.
reflect the true state of the device.
If the Full Flag is disabled through bits 12 and 11, the
device behaves as if it is full and ignores instructions to
Next Free address. Additionally, writes to the Page
Address register will be disabled. All other instructions
operate normally. Additionally, with the /FF disabled,
/FF=/FI. Normal operation of the device is with the /FF
enabled. The Full Flag Enable field has no effect on the
/FL Status Register bit. This bit always reflects the true
state of the device.
Control Register (CT)
The Control register is composed of a number of switches
that configure the LANCAM® MP, as shown in Table 9 on
page 24. It is written or read through DQ15–0 using a
TCO CT instruction on DQ31–16. On read cycles,
DQ31–16 will be the upper 16 bits of the Status register. If
bit 15 of the value written during a TCO CT is a 0, the
device is reset (and all other bits are ignored). See Table 5
for the Reset states. Bit 15 always reads back as a 0. A
write to the Control register causes an automatic compare
to occur (except in the case of a reset). Either the
Foreground or Background Control register will be active,
depending on which has been selected, and only the active
Control register will be written to or read from.
Control Register bits 8–6 control the CAM/RAM
partitioning. The CAM portion of each word may be sized
from a full 128 bits down to 32 bits in 32-bit increments.
The RAM portion can be at either end of the 128-bit word.
Compare masks may be selected by bits 5 and 4. Mask
Register 1, Mask Register 2, or neither may be selected to
mask compare operations. The Address register behavior
is controlled by bits 3 and 2, and may be set to increment,
decrement, or neither after a memory access. Bits 1 and 0
set the operating mode: Standard or Enhanced as shown in
Table 6 on page 12. The device will reset to Standard
mode and follow the operating responses in Table 6. When
operating in Enhanced mode, it is not necessary to unlock
the daisy chain with a NOP instruction before command or
data writes after a non-matching compare, as required in
Standard mode.
If the Match flag is disabled through bits 14 and 13, the
internal match condition, /MA(int), used to determine a
daisy-chained device’s response is forced HIGH as shown
in Table 6 on page 12, so that Case 6 is not possible,
effectively removing the device from the daisy chain. With
the Match flag disabled, /MF=/MI and operations directed
to Highest-priority Match locations are ignored. Normal
operation of the device is with the /MF enabled. The
Match Flag Enable field has no effect on the /MA or /MM
output pins or Status Register bits. These bits always
10
Rev. 2
MUSIC [ MUSIC SEMICONDUCTORS ]
