®
MU9C1965A LANCAM MP
Operational Characteristics
Standard Mode
Case
Internal
/EC(int)
Internal
/MA(int)
External
/MI
Device Select
Register
Command
Write1
Data
Write
Command
Read
Data
Read
YES3
YES3
NO
YES4
YES4
NO
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH
DS = PA
NO
YES
NO
NO
YES
NO
DS ≠ FFFFH and
DS ≠ PA
NO5
NO5
4
5
0
0
0
X
1
0
0
1
1
X
NO
NO
NO
NO
NO
NO
X
62
YES3
YES4
YES5
X
YES
Enhanced Mode
Case
Internal
/EC(int)
Internal
/MA(int)
External
/MI
Device Select
Register
Command
Write1
Data
Write
Command
Read
Data
Read
YES3
YES3
NO
YES4
YES4
NO
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH
DS = PA
NO
YES
NO
NO
YES
NO
DS ≠ FFFFH and
DS ≠ PA
YES3,6
YES3,6
YES3
YES4,7
YES4,7
YES4
NO5
NO5
4
5
0
0
0
0
1
0
0
X
1
X
X
X
NO
NO
62
YES5
YES
Notes:
1.
Exceptions are:
A) A write to the Device Select register is always active in all devices;
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.
If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.
2.
3.
4.
5.
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.
For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain (i.e., /FI LOW
and /FF HIGH) and NO if it does not.
6.
7.
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.
This is NO if the Persistent Destination is Memory at Highest-Priority match.
Table 6: Standard and Enhanced Mode Device Select Response
The Full Flag daisy chain causes only the device whose
/FI input is LOW and /FF output HIGH to respond to an
instruction using the Next Free address. After a reset, the
Next Free Address register is set to zero.
After a reset or a no match condition, the match address
bits will be all 1s.
Comparand Register (CR)
The 128-bit Comparand register is the default destination
for data writes and reads, using the Segment Control
register to select which 32-bit segment of the Comparand
register is to be loaded or read out. The persistent source
and destination for data writes and reads can be changed to
the mask registers or memory by SPS and SPD
instructions. During an automatic or forced compare, the
Comparand register is compared against the CAM portion
of all memory locations with the correct validity condition
simultaneously. Automatic compares always compare
against valid memory locations, while forced compares,
using CMP instructions, can compare against memory
locations tagged with any specific validity condition.
Status Register
The 32-bit Status register, shown in Table 12 on page 25,
is the default source for Command Read cycles. Bit 31 is
the internal Match flag, which will go LOW if a match
was found in this particular device. Bit 30 is the internal
Multiple Match flag, which will go LOW if a Multiple
match was detected. Bit 29 is the internal Full flag, which
will go LOW if the particular device has no empty
memory locations. Bits 28 and 27 are the Skip and Empty
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Skip and Empty bits will
read 11 until a read or move from memory has occurred.
The rest of the Status register contains the Page address of
the device and the address of the Highest-Priority match.
The Comparand register may be shifted one bit at a time to
12
Rev. 2
MUSIC [ MUSIC SEMICONDUCTORS ]
