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LQUEUE flags may be set for an entry that has changed
status. The user may qualify reads from AQUEUE and
LQUEUE with the appropriate ports match flag that will
be asserted if the data is valid.
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There are four sources of interrupts that will cause the INT
pin to be asserted: AQUEUE, LQUEUE, SWEX, and
PWEX. The appropriate enables must be set in the Config-
uration register to enable the interrupts.
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The interrupt service routine should read the appropriate
flag registers to determine the interrupt cause. The flags
are available individually or from the Address Index
register. The appropriate individual flag register must be
read in order to acknowledge the interrupt.
SWEX and PWEX interrupts are set when a write excep-
tion condition occurs. This occurs when two Write cycles
are pending in the device and there is only one space left.
The SWEX and PWEX flags indicate which port caused
the exception and which are available individually to the
processor. Both processor write exceptions are available in
the processor Address index port and the DOUT port
Address index word.
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AQUEUE and LQUEUE interrupts are set by an entry
being written into one or another of the queues. When the
flag register is read the interrupt is acknowledged. The
processor may read the LQUEUE and AQUEUE flags to
determine when all the entries are read from the appro-
priate queue. The interrupt will not be reasserted until a
queue has been emptied and then gets another entry. Note
that it is possible for learned entries to be aged and aged
entries to be learned. If this occurs the AQUEUE and
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Refer to IEEE Standard 1149.1 for information on using
the JTAG functions. See Table 4 for JTAG functions.
BSDL files are available; check the MUSIC Semiconduc-
tors website or contact MUSIC Technical Support.
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CLK periods to complete. Due to the internal design of the
MUAA RCP, pipelining is possible; therefore, further
operations can be performed while the DA search is being
done internally.
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This typical example shows the cycles that the MUAA
RCP would perform in multiport switch. The
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CAM/RAM partition is set to 48 bits CAM, 32 bits RAM.
Both the processor port and the synchronous port are 32
bits wide. The index and flags are programmed to be the
last word out of the DOUT port. The synchronous port has
priority. The LQUEUE and AQUEUE are enabled. The
CAM partition is used to store 48-bit MAC addresses and
the RAM partition used to store associated data to the
MAC address such as switch port and VLAN numbers.
Sync Port cycle2 is a learn on a frame SA (Source
address). At CLK3 the first word of CAM is loaded, at
CLK4 the second word is loaded (most significant 16 bits
discarded). At CLK5 the learn instruction is given along
with the word of RAM data that would contain the port ID
and other data associated with the SA.
At CLK6 the results of the search instruction issued in
cycle1 are available at the DOUT bus of the synchronous
port, as indicated by /DOUTVALID going active for a
CLK. The result of this cycle was a no-match condition as
/MF was not asserted LOW. Because the cycle was a DA
search and there was a no-match result, there will be no
data available on the DOUT bus. Typically in this situation
a switch would forward the frame to all ports or all ports
on the same VLAN.
Sync Port Cycle 1 is a search to lookup the port associated
with a frame DA (Destination address). At CLK1 the first
word (32 bits) of CAM search word is loaded. At CLK2
the last 16 bits of CAM search word is loaded and the
instruction “search” given. The most significant 16 bits of
the second word are discarded as the CAM partition is 48
bits wide. The results from the DA search will not be
available until CLK6 because the operation takes three
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