Geode™ CS4210
Operational Description
(Continued)
3.6
PHYSICAL REQUESTS
If the offset address is one of the following addresses, the
Physical Request controller directly handles quadlet reads.
Other requests shall be sent an ack_type_error.
1)
Config ROM header (1st quadlet of the Config ROM)
(FFFFF0000400h): Local register is ConfigROM-
header (see Section 4.4.5 "Configuration ROM Header
Bus ID (1st quadlet of the Bus_Info_Block)
(FFFFF0000404h): Local register is BusID (see Sec-
Bus options (2nd quadlet of the Bus_Info_Block)
(FFFFF0000408h): Local register is BusOptions (see
Global unique ID (3rd and 4th quadlets of the
Bus_Info_Block)
(FFFFF000040Ch
and
FFFFF0000410h): Local registers are GlobalIDHi and
GlobalIDLo (see Section 4.4.8 "Global Unique ID Reg-
Configuration
ROM
(FFFFF0000414h
to
FFFFF00007FFh). Mapped by the ConfigROMmap-
ping register to a 1 KB block of system memory (see
When a block or quadlet read or write request is received,
the CS4210 handles the operation automatically without
involving software if the offset address in the request
packet header meets a specific set of criteria listed below.
Requests that do not meet these criteria are directed to the
AR DMA Request context unless otherwise specified.
CS4210 registers which are written via physical access to
the CS4210 yield unspecified results. The CS4210 checks
to see if the offset address in the request packet header is
one of the following.
If the offset falls within the physical range, then the offset
address is used as the memory address for the block or
quadlet transaction. Physical range is defined by offsets
inclusively between a lower bound of 0h and an upper
bound of 0000_FFFF_FFFFh. If the high order 16-bits of
the offset address is 0000h, then the lower 32 bits of the
offset address are used as the memory address for the
block or quadlet transaction.
Lock transactions and block transactions with a non-zero
extended tcode are not supported in this address space,
instead they are diverted to the AR DMA Request context.
For read requests, the information needed to formulate the
response packet is passed to the Physical Response Unit.
Requests are only accepted if the source node ID of the
request has a corresponding bit in the Asynchronous
Request Filter registers and Physical Request Filter regis-
ters (see Section 4.4.23 "Physical Request Filter Regis-
If the offset address selects one of the following addresses,
the physical request unit directly handles quadlet compare-
swaps and quadlet reads. Other requests are sent an
ack_type_error (see Table 3-7 on page 20.)
1)
2)
3)
4)
BUS_MANAGER_ID (FFFFF000021Ch):
Local register is nscBusmgrID (BAR1+Offset 60h).
BANDWIDTH_AVAILABLE (FFFFF0000220h):
Local register is nscBandwAvai (BAR1+Offset 64h).
CHANNELS_AVAILABLE_HI (FFFFF0000224h):
Local register is nscChanAvailHi (BAR1+Offset 68h).
CHANNELS_AVAILABLE_LO (FFFFF0000228h):
Local register is nscChanAvailLo (BAR1+Offset 6Ch).
2)
3)
4)
5)
For information about ack codes for write requests, see
3.6.1 Filtering Physical Requests
Software can control which nodes it receives packets from
by utilizing the asynchronous filter registers. There are two
registers, one for filtering out all requests from a specified
set of nodes (AsynchronousRequestFilter register) and one
for filtering out physical requests from a specified set of
nodes (PhysicalRequestFilter register). The settings in both
registers have a direct impact on how the AR DMA
Request context is used (e.g., disabling only physical
receives from a node causes all request packets from that
node to be routed to the AR DMA Request context). The
usage and interrelationship between these registers is
described in Section 4.4.22 "Asynchronous Request Filter
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