LM93
16.0 Registers
16.10.1 Register ECh
Register
Address
ECh
Read/
Write
R/W
(Continued)
16.10 OTHER MASK REGISTERS
GPI Error Mask
Register
Name
GPI Error
Mask
Bit
0
1
2
3
4
5
6
7
Name
GPI0_MSK
GPI1_MSK
GPI2_MSK
GPI3_MSK
GPI4_MSK
GPI5_MSK
GPI6_MSK
GPI7_MSK
Bit 7
GPI7
_MSK
Bit 6
GPI6
_MSK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 5
GPI5
_MSK
Bit 4
GPI4
_MSK
Bit 3
GPI3
_MSK
Description
When this bit is set, GPI0 error events are masked.
When this bit is set, GPI1 error events are masked.
When this bit is set, GPI2 error events are masked.
When this bit is set, GPI3 error events are masked.
When this bit is set, GPI4 error events are masked.
When this bit is set, GPI5 error events are masked.
When this bit is set, GPI6 error events are masked.
When this bit is set, GPI7 error events are masked.
Bit 2
GPI2
_MSK
Bit 1
GPI1
_MSK
Bit 0
GPI0
_MSK
Default
Value
FFh
These bits mask the corresponding bits in the B_ and H_GPI Error Status Registers. They do not effect the GPI State register.
16.10.2 Register EDh Miscellaneous Error Mask
Register
Address
EDh
Read/
Write
R/W
Register
Name
Miscellaneous
Error Mask
Name
VRD1_MSK
VRD2_MSK
SCSI1_MSK
SCSI2_MSK
DVccp1_MSK
DVccp2_MSK
RES
Bit 7
Bit 6
Bit 5
DVccp2
_MSK
Bit 4
DVccp1
_MSK
Bit 3
SCSI2
_MSK
Bit 2
SCSI1
_MSK
Bit 1
VRD2
_MSK
Bit 0
VRD1
_MSK
Default
Value
3Fh
RES
Bit
0
1
2
3
4
5
7:6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
When this bit is set, VRD1_HOT error events are masked.
When this bit is set, VRD2_HOT error events are masked.
When this bit is set, SCSI_TERM1 error events are masked.
When this bit is set, SCSI_TERM2 error events are masked.
When this bit is set, dynamic Vccp limit error events for
AD_IN7 (CPU1) are masked.
When this bit is set, dynamic Vccp limit error events for
AD_IN8 (CPU2) are masked.
Reserved
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