AC Electrical Characteristics
The following limits apply for +3.0 VDC to +3.6 VDC, unless otherwise noted. Bold face limits apply for TA = TJ = TMIN to
TMAX of the operating range; all other limits TA = TJ = 25˚C unless otherwire noted.
Typical
Limits
Units
Symbol
Parameter
Conditions
(Note 9) (Note 10) (Limits)
FAN RPM-TO-DIGITAL CHARACTERISTICS
Counter Resolution
14
2
bits
Number of fan tach pulses count is
based on
pulses
Counter Frequency
22.5
kHz
Accuracy
6
% (max)
PWM OUTPUT CHARACTERISTICS
Frequency Tolerances
6
6
% (max)
% (max)
Duty-Cycle Tolerance
2
RESET INPUT/OUTPUT CHARACTERISTICS
Output Pulse Width
250
330
10
ms (min)
ms (max)
µs (min)
µs (max)
Upon Power Up
Minimum Input Pulse Width
Reset Output Fall Time
1.6V to 0.4V Logic Levels
1
SMBUS TIMING CHARACTERISTICS
fSMBCLK
SMBCLK (Clock) Clock Frequency
10
100
kHz (min)
kHz (max)
tBUF
SMBus Free Time between Stop and
Start Conditions
4.7
µs (min)
tHD;STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
4.0
µs (min)
tSU;STA
tSU;STO
tSU;DAT
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Input Setup Time to SMBCLK
High
4.7
4.0
µs (min)
µs (min)
250
ns (min)
tHD;DAT
tLOW
Data Output Hold Time after SMBCLK
Low
300
930
4.7
50
ns (min)
ns (max)
µs (min)
µs (max)
µs (min)
µs (max)
µs (max)
ns (max)
ms
SMBCLK Low Period
tHIGH
SMBCLK High Period
4.0
50
tR
Rise Time
1
tF
Fall Time
300
tTIMEOUT
Timeout
31
SMBDAT or SMBCLK low
time required to
25
35
ms (min)
ms (max)
reset the Serial Bus
Interface to the Idle State
Time in which a device must be
operational after power-on reset
Capacitance Load on SMBCLK and
SMBDAT
>
tPOR
CL
VDD +2.8V
500
400
ms (max)
pF (max)
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