30
t
ADS
t
AH
t
AR
t
AS
t
AW
t
CH
t
CS
t
CSR
t
CSW
t
DH
t
DS
t
HZ
t
MR
t
RA
t
RC
t
RCS
t
RD
t
RDD
t
RVD
t
WA
t
WC
t
WCS
t
WR
t
XH
t
XL
RC
WC
N
t
BHD
t
BLD
t
HW
t
LW
AC Electrical Characteristics
T
A
e
0 C to
a
70 C
Parameter
Address Strobe Width
Address Hold Time
RD RD Delay from Address
Address Setup Time
WR WR Delay from Address
Chip Select Hold Time
Chip Select Setup Time
RD RD Delay from Chip Select
WR WR Delay from Select
Data Hold Time
Data Setup Time
RD RD to Floating Data Delay
Master Reset Pulse Width
Address Hold Time from RD RD
Read Cycle Delay
Chip Select Hold Time from RD RD
RD RD Strobe Width
RD RD to Driver Enable Disable
Delay from RD RD to Data
Address Hold Time from WR WR
Write Cycle Delay
Chip Select Hold Time from WR WR
WR WR Strobe Width
Duration of Clock High Pulse
Duration of Clock Low Pulse
Read Cycle
e
t
AR
a
t
RD
a
t
RC
Write Cycle
e
t
AW
a
t
WR
a
t
WC
Baud Divisor
Baud Output Positive Edge Delay
Baud Output Negative Edge Delay
Baud Output Up Time
Baud Output Down Time
Delay from Active Edge
of RD to Reset Interrupt
Delay from RD RD
(RD RBR or RD LSR)
to Reset Interrupt
Delay from RD RBR
to RXRDY Inactive
Delay from RCLK to Sample Time
Delay from Stop to Set Interrupt
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
V
DD
e a
5V
g
10%
Min
60
0
30
60
30
0
60
30
30
30
30
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
ns
ns
ns
ns
ns
ns
60
60
20
150
20
100
55
55
280
280
1
2
16
b
1
175
175
75
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Conditions
100 pF loading (Note 3)
0
5000
20
125
20
125
100 pF loading (Note 3)
100 pF loading
(Note 1)
External Clock (8 Max )
External Clock (8 Max )
Baud Generator
100 pF Load
100 pF Load
f
X
e
8
d
2 100 pF Load
f
X
e
8
d
2 100 pF Load
Receiver
t
RAI
t
RINT
ns
100 pF Load
1000
290
2000
1
ns
ns
ns
RCLK
Cycles
t
RXI
t
SCD
t
SINT
Note 1
Applicable only when ADS is tied low
Note 2
In the FIFO mode (FCR0
e
1) the trigger level interrupts the receiver data available indication the active RXRDY indication and the overrun error indication
will be delayed 3 RCLKs Status indicators (PE FE BI) will be delayed 3 RCLKs after the first byte has been received For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive Timeout interrupt is delayed 8 RCLKs
Note 3
Charge and discharge time is determined by V
OL
V
OH
and the external loading
Note 4
These specifications are preliminary
4
NSC [ NATIONAL SEMICONDUCTOR ]
