30
AC Electrical Characteristics
(Continued)
Parameter
Conditions
Min
Max
Units
Symbol
Transmitter
t
HR
t
IR
t
IRS
t
SI
t
STI
t
SXA
t
WXI
Modem Control
t
MDO
t
RIM
t
SIM
Delay from WR WR (WR THR)
to Reset Interrupt
Delay from RD RD (RD IIR) to Reset
Interrupt (THRE)
Delay from Initial INTR Reset to Transmit
Start
Delay from Initial Write to Interrupt
Delay from Stop to Interrupt (THRE)
Delay from Start to TXRDY active
Delay from Write to TXRDY inactive
100 pF Load
100 pF Load
175
250
8
24
24
8
8
195
ns
ns
BAUDOUT
Cycles
BAUDOUT
Cycles
BAUDOUT
Cycles
BAUDOUT
Cycles
ns
(Note 1)
(Note 1)
100 pF Load
100 pF Load
16
8
Delay from WR WR (WR MCR) to
Output
Delay from RD RD to Reset Interrupt
(RD MSR)
Delay from MODEM Input to Set Interrupt
100 pF Load
100 pF Load
100 pF Load
200
250
250
ns
ns
ns
Note 1
This delay will be lengthened by 1 character time minus the last stop bit time if the transmitter interrupt delay circuit is active (See FIFO Interrupt Mode
Operation)
Note 2
These specifications are preliminary
40
Timing Waveforms
(All timings are referenced to valid 0 and valid 1)
External Clock Input (24 0 MHz Max )
AC Test Points
TL C 8652 –3
TL C 8652 – 2
Note 1
The 2 4V and 0 4V levels are the voltages that the inputs are driven to during AC testing
Note 2
The 2 0V and 0 8V levels are the voltages at which the timing tests are made
BAUDOUT Timing
TL C 8652 – 4
5
NSC [ NATIONAL SEMICONDUCTOR ]
