Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
When the set lock-bit operation is complete, SR.4 should be checked for any error.
When the clear lock-bit operation is complete, SR.5 should be checked for any error.
Errors bits must be cleared using the Clear Status Register command.
Block lock-bit status can be determined by first issuing the Read Device Information
command, and then reading from <block base address> + 02h. DQ0 indicates the lock
status of the addressed block (0 = unlocked, 1 = locked).
9.7.2
9.7.3
Configurable Block Locking
One of the unique new features on the Numonyx™ Embedded Flash Memory (J3 v D,
Monolithic) ,which did not exist on the previous generations of this product family, is
the ability to protect and/or secure the user’s system by offering multiple level of
securities: Non-Volatile Temporary; Non-Volatile Semi-Permanent or Non-Volatile
Permanent. For additional information and collateral request, please contact your filed
representative.
OTP Protection Registers
Numonyx™ Embedded Flash Memory (J3 v D, Monolithic) includes a 128-bit Protection
Register (PR) that can be used to increase the security of a system design. For
example, the number contained in the PR can be used to “match” the flash component
with other system components such as the CPU or ASIC, hence preventing device
substitution.
The 128-bits of the PR are divided into two 64-bit segments:
• One segment is programmed at the Numonyx factory with a unique unalterable 64-
bit number.
• The other segment is left blank for customer designers to program as desired. Once
the customer segment is programmed, it can be locked to prevent further
programming.
9.7.4
9.7.5
Reading the OTP Protection Register
The Protection Register is read in Identification Read mode. The device is switched to
this mode by issuing the Read Identifier command (0090h). Once in this mode, read
cycles from addresses shown in Table 29, “Word-Wide Protection Register Addressing”
or Table 30, “Byte-Wide Protection Register Addressing” retrieve the specified
information. To return to Read Array mode, write the Read Array command (00FFh).
Programming the OTP Protection Register
PR bits are programmed using the two-cycle Protection Program command. The 64-bit
number is programmed 16 bits at a time for word-wide configuration and eight bits at a
time for byte-wide configuration. First write the Protection Program Setup command,
00C0h. The next write to the device will latch in address and data and program the
specified location. The allowable addresses are shown in Table 29, “Word-Wide
Protection Register Addressing” on page 45 or Table 30, “Byte-Wide Protection Register
Addressing” on page 46. See Figure 27, “Protection Register Programming Flowchart”
on page 57. Any attempt to address Protection Program commands outside the defined
PR address space will result in a Status Register error (SR.4 will be set). Attempting to
program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will
be set).
Datasheet
44
December 2007
316577-06
NUMONYX [ NUMONYX B.V ]
