Numonyx™ Embedded Flash Memory (J3 v D, Monolithic)
Table 25: Valid Commands During Suspend (Sheet 2 of 2)
Device Command
Program Suspend
Erase Suspend
Lock Block
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Unlock Block
Program OTP Register
During Suspend, array-read operations are not allowed in blocks being erased or
programmed.
A block-erase under program-suspend is not allowed. However, word-program under
erase-suspend is allowed, and can be suspended. This results in a simultaneous erase-
suspend/ program-suspend condition, indicated by SR[7,6,2] = 1.
To resume a suspended program or erase operation, issue the Resume command to
any device address. The read mode of the device is automatically changed to Read
Status Register. The operation continues where it left off, STS (in RY/BY# mode) goes
low, and the respective Status Register bits are cleared.
When the Resume command is issued during a simultaneous erase-suspend/ program-
suspend condition, the programming operation is resumed first. Upon completion of the
programming operation, the Status Register should be checked for any errors, and
cleared. The resume command must be issued again to complete the erase operation.
Upon completion of the erase operation, the Status Register should be checked for any
errors, and cleared.
9.6
Status Signal
The STATUS (STS) signal can be configured to different states using the STS
Configuration command (Table 26). Once the STS signal has been configured, it
remains in that configuration until another Configuration command is issued or RP# is
asserted low. Initially, the STS signal defaults to RY/BY# operation where RY/BY# low
indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready
for a new operation or suspended. Table 27 displays possible STS configurations.
Table 26: STS Configuration Register
Setup Write Cycle
Address Bus Data Bus
Device Address 00B8h
Confirm Write Cycle
Command
Address Bus
Device Address
Data Bus
STS Configuration
Register Data
To reconfigure the STATUS (STS) signal to other modes, the Configuration command is
given followed by the desired configuration code. The three alternate configurations are
all pulse mode for use as a system interrupt as described in the following paragraphs.
For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1
controls Program Complete interrupt pulse. Supplying the 00h configuration code with
the Configuration command resets the STS signal to the default RY/BY# level mode.
The Configuration command may only be given when the device is not busy or
suspended. Check SR.7 for device status. An invalid configuration code will result in
SR.4 and SR.5 being set.
Note:
STS Pulse mode is not supported in the Clear Lock Bits and Set Lock Bit commands.
Datasheet
42
December 2007
316577-06
NUMONYX [ NUMONYX B.V ]
