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JS48F4400P0Z3W0 参数 Datasheet PDF下载

JS48F4400P0Z3W0图片预览
型号: JS48F4400P0Z3W0
PDF下载: 下载PDF文件 查看货源
内容描述: StrataFlash㈢蜂窝内存 [StrataFlash㈢ Cellular Memory]
分类和应用: 蜂窝
文件页数/大小: 139 页 / 2133 K
品牌: NUMONYX [ NUMONYX B.V ]
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Numonyx™ StrataFlash® Cellular Memory (M18)  
2.0  
Functional Description  
2.1  
Product Overview  
The Numonyx™ StrataFlash® Cellular Memory (M18) device provides high read and  
write performance at low voltage on a 16-bit data bus.  
The flash memory device has a multi-partition architecture with read-while-program  
and read-while-erase capability.  
The device supports synchronous burst reads up to 108 MHz using ADV# and CLK  
address-latching on some litho/density combinations and up to 133 MHz using CLK  
address-latching only on some litho/density combinations. It is listed below in the  
following table.  
Table 4:  
M18 Product Litho/Density/Frequency Combinations  
Litho (nm)  
Density (Mbit)  
Supports frequency up to (MHz)  
Sync read address-latching  
CLK-latching  
256  
512  
133  
108  
133  
133  
133  
108  
133  
90  
ADV#- and CLK-latching  
CLK-latching  
128  
256  
CLK-latching  
65  
512  
CLK-latching  
1024  
1024  
ADV#- and CLK-latching  
CLK-latching  
In continuous-burst mode, a data Read can traverse partition boundaries.  
Upon initial power-up or return from reset, the device defaults to asynchronous array-  
read mode. Synchronous burst-mode reads are enabled by programming the Read  
Configuration Register. In synchronous burst mode, output data is synchronized with a  
user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory  
synchronization.  
Designed for low-voltage applications, the device supports read operations with VCC at  
1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. VCC and VPP can  
be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a  
dedicated VPP connection provides complete data protection when VPP is less than  
VPPLK  
.
A Status Register provides status and error conditions of erase and program  
operations.  
One-Time-Programmable (OTP) registers allow unique flash device identification that  
can be used to increase flash content security. Also, the individual block-lock feature  
provides zero-latency block locking and unlocking to protect against unwanted program  
or erase of the array.  
The flash memory device offers three power savings features:  
• Automatic Power Savings (APS) mode: The device automatically enters APS  
following a read-cycle completion.  
• Standby mode: Standby is initiated when the system deselects the device by  
deasserting CE#.  
Datasheet  
10  
April 2008  
309823-10