M28W160CT, M28W160CB
Table 30. Primary Algorithm-Specific Extended Query Table
Offset
Data
Description
Value
(1)
P = 35h
(P+0)h = 35h
(P+1)h = 36h
(P+2)h = 37h
(P+3)h = 38h
(P+4)h = 39h
(P+5)h = 3Ah
(P+6)h = 3Bh
(P+7)h = 3Ch
(P+8)h = 3Dh
0050h
0052h
0049h
0031h
0030h
0066h
0000h
0000h
0000h
"P"
"R"
"I"
Primary Algorithm extended Query table unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
"1"
"0"
Extended Query table contents for Primary Algorithm. Address (P+5)h
contains less significant byte.
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
bit 8
Chip Erase supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Suspend Erase supported
Suspend Program supported
Legacy Lock/Unlock supported
Queued Erase supported
No
Yes
Yes
No
Instant individual block locking supported (1 = Yes, 0 = No)
No
Protection bits supported
Page mode read supported
Synchronous read supported
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
(1 = Yes, 0 = No)
Yes
Yes
No
bit 31 to 9 Reserved; undefined bits are ‘0’
No
(P+9)h = 3Eh
0001h
Supported Functions after Suspend
Read Array, Read Status Register and CFI Query are always supported
during Erase or Program operation
bit 0
bit 7 to 1
Program supported after Erase Suspend (1 = Yes, 0 = No)
Reserved; undefined bits are ‘0’
Yes
(P+A)h = 3Fh
(P+B)h = 40h
0003h
0000h
Block Lock Status
Defines which bits in the Block Status Register section of the Query are
implemented.
Address (P+A)h contains less significant byte
bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)
bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)
bit 15 to 2 Reserved for future use; undefined bits are ‘0’
Yes
Yes
(P+C)h = 41h
(P+D)h = 42h
(P+E)h = 43h
0030h
00C0h
0001h
V
V
Logic Supply Optimum Program/Erase voltage (highest performance)
3V
12V
01
DD
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
Supply Optimum Program/Erase voltage
PP
bit 7 to 4
bit 3 to 0
HEX value in volts
BCD value in 100 mV
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
(P+F)h = 44h
(P+10)h = 45h
(P+11)h = 46h
(P+12)h = 47h
0080h
0000h
0003h
0003h
Protection Field 1: Protection Description
80h
00h
This field describes user-available. One Time Programmable (OTP)
Protection register bytes. Some are pre-programmed with device unique
serial numbers. Others are user programmable. Bits 0–15 point to the
Protection register Lock byte, the section’s first byte.
8 Byte
8 Byte
The following bytes are factory pre-programmed and user-programmable.
bit 0 to 7
Lock/bytes JEDEC-plane physical low address
bit 8 to 15
Lock/bytes JEDEC-plane physical high address
n
bit 16 to 23 "n" such that 2 = factory pre-programmed bytes
n
bit 24 to 31 "n" such that 2 = user programmable bytes
(P+13)h = 48h
Reserved
Note: 1. See Table 27, offset 15 for P pointer definition.
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NUMONYX [ NUMONYX B.V ]
