M29W640GH, M29W640GL, M29W640GT, M29W640GB
Figure 6. Write Enable controlled Program waveforms (8-bit mode)
Command Interface
3rd cycle
4th cycle
PA
Read cycle
Data Polling
PA
tAVAV
tAVAV
A0-A20/
A–1
555h
tAVWL
tWLAX
tELQV
tELWL
tGHWL
tWHEH
E
tGLQV
G
tWLWH
tWHWL
W
tDVWH
tWHWH1
DQ7
tGHQZ
tAXQX
DQ0-DQ7/
DQ8-DQ15
D
AOh
PD
tWHDX
D
OUT
OUT
AI12779
1. Only the third and fourth cycles of the Program command are represented. The Program command is followed by the check
of Status register Data Polling bit and by a read operation that outputs the data, DOUT, programmed by the previous
Program command.
2. PA is address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (see Section 5.1: Data Polling Bit (DQ7)).
4. Addresses differ in x8 mode.
5. See Table 19: Write ac characteristics and Table 18: Read ac characteristics for details on the timings.
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NUMONYX [ NUMONYX B.V ]
