NXP Semiconductors
TDA6650TT; TDA6651TT
5 V mixer/oscillator and low noise PLL synthesizer
50
µs
START
ADDRESS DIVIDER
BYTE
BYTE 1
DIVIDER CONTROL CONTROL CONTROL CONTROL
STOP
BYTE 2
BYTE 1
BYTE 2
BYTE 1
BYTE 2
I
2
C-bus transmission dedicated to
the MOPLL
START
ADDRESS
BYTE
I
2
C-bus transmission
dedicated to
another IC
fce921
Fig 4. Example of I
2
C-bus transmission frame
Table 6.
Name
Address byte
Divider byte 1 (DB1)
Divider byte 2 (DB2)
Control byte 1 (CB1);
see
Control byte 2 (CB2)
[1]
I
2
C-bus write data format
Byte
1
2
3
4
5
Bit
MSB
1
0
N7
1
1
CP2
1
N14
N6
T/A = 1
T/A = 0
CP1
0
N13
N5
T2
0
CP0
0
N12
N4
T1
0
BS5
0
N11
N3
T0
ATC
BS4
MA1
N10
N2
R2
AL2
BS3
MA0
N9
N1
R1
AL1
BS2
LSB
R/W = 0 A
N8
N0
R0
AL0
BS1
A
A
A
A
A
Ack
MSB is transmitted first.
Table 7.
Bit
A
Description of write data format bits
Description
acknowledge
programmable address bits; see
logic 0 for write mode
programmable LO frequency;
N = N14
×
2
14
+ N13
×
2
13
+ N12
×
2
12
+ ... + N1
×
2
1
+ N0
test/AGC bit
T/A = 0: the next 6 bits sent are AGC settings
T/A = 1: the next 6 bits sent are test and reference divider ratio settings
MA1 and MA0
R/W
N14 to N0
T/A
T2, T1 and T0
R2, R1 and R0
ATC
test bits; see
reference divider ratio and programmable frequency step; see
AGC current setting and time constant; capacitor on pin AGC = 150 nF
ATC = 0: AGC current = 220 nA; AGC time constant = 2 s
ATC = 1: AGC current = 9
µA;
AGC time constant = 50 ms
AL2, AL1 and AL0
CP2, CP1 and CP0
AGC take-over point bits; see
charge pump current; see
BS5, BS4, BS3, BS2 PMOS ports control bits
and BS1
BSn = 0: corresponding port is off, high-impedance state (status at
power-on reset)
BSn = 1: corresponding port is on; V
O
= V
CC
−
V
DS(sat)
TDA6650TT_6651TT_5
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 — 10 January 2007
9 of 54
PHILIPS [ NXP SEMICONDUCTORS ]
