JLC1562B
Power−On
Reset
SDA
8 Bit
I2C Bus Controller
6 Bit
Latch
6−Bit
DAC
Latch
SCL
V
DD
Write Buffer
P7
P6
P5
P4
P3
P2
P1
P0
VDAC
A0
A1
A2
Shift Register (PISO) (SIPO)
1/2 V
CC
Comp.
A
(C5−C7)
Latch
5 Bit
5 Bit
3 Bit
Comp.
B
(C0−C4)
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 V
DD
and selects 1/2 V
DD
for Comparator “B” threshold.
Figure 2. Block Diagram
Pin 1
VDAC
Comparator “B”
V
ref
V
DD
16 X R
65
R
64
R
63
Write Data (2)
V
ref
Selector
Bit D6 of Write Data (2)
R
40
D6
1
0
V
ref
Value
V
ref
= VDAC
V
+
40 V
ref
80 DD
R
39
Write Data (2)
D5
1
R
2
D4
1
D3
1
D2
1
•
•
•
•
1LSB
+
1 V
80 DD
0
0
0
0
0
0
0
0
0
0
1
0
D1
1
D0
1
V
ref
64 V
80 DD
•
•
•
•
2 V
80 DD
1 V
80 DD
R
1
GND
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
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